JPS61122582A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent such trouble that plural FFs send outputs to an internal or external bus during a scan test to cause a bus fight by providing a logical circuit, scanning FFs, an input or output circuit, logical gates, etc. CONSTITUTION:The internal bus 10, internal bus drives 12-1-12-3 and 14-1 and 14-2, scanning FFs 16-1-16-n and 16-N, a scan data input pin 18, a scan data output pin 20, etc., are provided. All the scanning FFs are connected in series between the input pin 18 and output pin 20 in scan test mode and an 'H' signal is applied to a scan test mode signal input pin 24. Consequently, OR gate outputs of all internal bus drivers 12-1-12-3 and 14-1 and 14-2 go up to 'H', respective buffers become inactive, and their outputs enter a high impedance state. Therefore, such trouble that plural bus drivers operate in scan mode to cause a bus fight is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having the function of performing a scan test.

[Conventional technology]

Scan testing is well known as a testing method for large-scale integrated circuits (LSI). Normally, an LSI is equipped with scan input, scan output, A clock, B clock, and scan test bins, and these are used to set the data for all seven flip-flops and to control the logic circuit between the flip-flops. It is something to test.

FIG. 4 shows the concept at the time of this scan test. In scan test mode, all 7 lip 70 lip FIF
11 to FIFN are connected in series, and the inputs applied from the scan data input bins are sequentially set to each flip-flop. After performing logical operations on the outputs of these flip-flops in the arithmetic circuit ALU, the data is set in the next flip-flop using the system clock, and the scan data is transferred again to obtain the operation results from the scan data output bin η). A test will be conducted.

The scan free lag frog normally has the function as shown in FIG. That is, data human power Din.

During normal operation, glue is input CK, scan data input S
in @ Aalk, which is the input for the scan lock.

Ba1k, with scan output and common output Q, Q^
Ru. When in scan test mode, the flea is Aalk, Bclk.
nSin, Q, and Q are used, CK is held in a non-write state, and %Din is ignored. In the non-scan test mode, that is, during normal operation, Ac1k and Bclk are held in the non-scan state.
is ignored. The scan outputs share the normal operation outputs Q and Q. This is scan test mode Tokiko Q,
If T is used to hold Q, the circuit will be held even in normal operation, or the number of gates will be 1.5 times as many. The nine-scan flip-frog may include a clear input CLR and a preset input PR.

LSI6 with scan test function as mentioned above
+By the way, the conventional bus drive circuit is
As shown in the figure, regardless of whether or not the scan test mode is active, the bus control signal Ct is only in the active state [16 or inactive state]. .

[Problems that the invention attempts to solve]

According to such conventional technology, during the scan test mode, data is simultaneously output to the bus from a plurality of 7-lips 70-tubes, resulting in a so-called bus fight situation, which may cause an excessive current to flow.

[The tth way to solve the problem]

The features of the present invention that solve the above-mentioned disadvantages include a logic circuit;
a plurality of scanning flip-flops for setting test data for the logic circuit during a scan test;
a human power or output circuit connected between the logic circuit and an internal bus or an external bus;

The input or output signal of the logic circuit is provided with a logic gate that performs logic between a control signal and a scan mode signal in response, and the output of the logic gate determines the operation or non-operation of the input or output circuit. The input or output circuit is controlled to be inactive during the scan test.

[For production]

Since the input/output section has a high impedance during a scan test, there is no problem such as L5, where signals are output from a plurality of flip-flops to an internal bus or an external bus and a bus fight occurs during a scan test.

〔Example〕

Figure fFI1 is a circuit diagram of an embodiment of the present invention. This embodiment allows logic to be established between a scan test mode signal and a control signal for a bus driver connected to an internal bus of an LSI.

Also shown is a case where the logic circuit under test is an ALU. In the figure, 10 is an internal bus and 12-.

〜12-3 and 14-凰〜14-2 are internal bus drivers connected to the internal bus 1o, 16-1 to 16n, 16
N is a scan 7 lip-flop, 17 is ALo which is the circuit under test, and 18 is a scan data input bin.

20 is a scan data output bin. In addition, each scan flip-flop has a scan clock manually operated by Aalk~
Balk, normal operation clock Kugata CK, etc. are omitted from the illustration. Note that during normal operation, the scan 7 rig 70 tabs 16-1 to 16-n ODin terminals ζ receive data from other logic circuits (pre-stage circuits of the ALU), and the input data is input to the output side of the flip-flop. From ALUI
7fC is supplied.

Further, each output of the human LU 17 is supplied to the Din terminal layer of the scan flip frogs 16-Hat to 16-N, respectively. Furthermore, the NoQ terminals of each of the scan flip-flops 16-1 to 16-16-1 are connected to the Sin terminals of the scan flip-flops in the next stage, as in the circuit of FIG.

Each internal bus driver 12-1 to 12-8 and 14-1 to
14-2 includes a buffer and an OR gate whose output is connected to its control terminal. The output of each scan flip-flop is connected to these OR gates. For example, the outputs of the scan flip-flops 16-1, 16-x are sent to each internal bus driver 14-□ via gate circuits 22-1e22-sf, respectively.

The input of the OR gate 14-2 is connected. This is because during normal operation (this is because it is necessary to control the logic between the ALU input signal and other signals and control 14-t, it, with nine signals.The other input of each OR gate is scanned). Test mode signal input pin 24 is connected.

In scan test mode, scan data enters mold/18
All the scan flips 70 are connected in series between the scan test mode signal input pin 24 and the scan data output pin 20. The OR gate outputs of internal bus drivers 12-0 to 12-3 and 14-1 to 14-2 become 1H''.

Each buffer is inactive and its output is in a high impedance state. As a result, the inconvenience that a plurality of bus drivers operate during the scan mode, resulting in a bus fight and excessive current flowing, is eliminated. In the prior art, for example, 7 lip-flops 16-8 and 16
-z+koL" data is set to 9, this is sent to the internal bus drivers 14-8 and 14-2 via the gate circuits 22-! and 22-3, respectively, and these bus drivers are both in the operating state. As a result, direct current will flow in the case of direct current.(Specifically.

One of the drivers connected to the common bus is lol
If the driver outputs L1 and the other driver outputs L1, a DC current will flow. ) t7+2. Clear input CI of flip-flop 16-n
, 'R is determined by the output of the flip-flop 16-3, then the flip-flop 16-3
When the flip-flop 6-3 is set to "L" and G, the data of the flip-flop 16-n is cleared, and there is a possibility that the normal scan data will be erased. This ninth, or gate 2
6 is set, the scan test mode is set to ``H'' (i
Applying the number to this, 7 rigs, 116
-n's clear input is maintained at H''i.A similar idea is applied to the clear manual input and preset input of flip-flop 33, as shown in the second section.- By setting 27 and 29 in each input, the clear input ετπ and the preset input 1 will continue to be at H1 by setting C to H'' (in the scan test mode). In addition, OR gate 290 input p
K GX is supplied from the output side of a scan flip-flop, for example.

Referring to FIG. 1, 28 is a bus bin connected to an external bus, and 30 is a bidirectional input/output circuit for the external bus. When the buffer of this bidirectional input/output circuit 30 is controlled by the output of the 7-lip flop 116-n, during a scan test, the set contents of the flip-flop 16-n (this input/output circuit changes to the input state accordingly). Therefore, an OR gate 32 is provided, and when the Hg signal is applied to this OR gate 32 in the scan test mode, it becomes a high impedance state and enters the input state. In addition, in the scan test mode, the bus via 28i-external can be set to ``l'' or ``L''.

However, if the clock of a flip-flop is in logical bits with the output of another 7 flip-flops, there is a risk that this clock may change (during a scan test). Like, flip-flop 34
An OR gate 36 is provided at the gate input, and a signal H* is applied to the OR gate 36 during the scan test mode. For one thing or two, in the scan test mode, the clock input of the 7-lip-frog 34 is CK always at 1H''.

In the above explanation and examples, an OR gate is used as a logic control gate during a scan test, but it is clear that other gates such as an AND gate may also be used.

〔Effect of the invention〕

According to the present invention, since the input/output section becomes high impedance during a scan test, outputs are output from a plurality of 7 lip-flops to an internal bus or an external bus during a scan test, causing a bus fight and causing an overcurrent to flow. The inconvenience will go away without any modification. Additionally, power consumption can be reduced and cycle time can also be shortened.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a diagram showing an example in which the clear input section and preset input section are applied, and Figure 3 is a diagram showing an example of 7'C applied to the clock input section. Figure, 4th
7 to 7 are explanatory diagrams of the prior art. 10...Internal bus, 12-1 to 12-i e
14-t~14-z ・--- Internal bus driver,
l 6-1-16-IN e16-N...Scan flip-flop, 17...ALU%1
8...Scan data input bin, 20...
...Scan data output pin, 24...Scan test mode signal input pin, 26.27゜29.32
．． 36...OR gate, 28...Bus pin, 30...Bidirectional input/output circuit. Figure 3 4th country 5th country

Claims (1)

[Claims] a logic circuit, a plurality of scan flip-flops for setting test data for the logic circuit during a scan test, an input or output circuit connected between the logic circuit and an internal bus or an external bus; A logic gate is provided that outputs the logic between a control signal responsive to an input or output signal of the logic circuit and a scan mode signal, and the output of the logic gate controls the operation or non-operation of the input or output circuit. A semiconductor integrated circuit device, wherein the input or output circuit is rendered inactive during the scan test.