JPS61121620A - Error protection circuit of dpcm decoder - Google Patents

Abstract

PURPOSE:To suppress noise even with overflow due to transmission error while keeping simple constitution by providing an inverse quantizing ROM, an adder, a forecast device and a D/A converter and a circuit detecting overflow from 2 inputs and an output of the adder, replacing the adder output into a constant in response to the output of the detection circuit and applying the result to the fore case device. CONSTITUTION:Since an overlow detection output is generated thereby giving an output to a forecast device while being replaced into an upper or a lower limit when there is an error and overflow takes place, a decoded output is clipped at upper and lower limits and a jump to an opposite peak is lost, then a large noise is prevented. For example, a detected output 54 is fed to a clip circuit 6 to replace the output data of an adder 2 is replaced into an upper/ lower limit data and outputted to an analog output terminal through a forecast device 3 and a D/A converter 4. An analog output waveform is shown in waveform diagram, and even if an error takes place and the signal reaches the limits, noise generation is prevented.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to transmission band compression of audio signals, etc.
(Differential Pulse Code
Modulation) This relates to the configuration of the error protection circuit of the decoder.

BACKGROUND ART A DPCM decoder is considered as a local circuit of a DPCM encoder, and has been developed as a band compression technique for various types of images and the like. (Edited by the Institute of Electronics and Communication Engineers, Electronic Communication...Ndopunoku No. 16)
Edited by Section 3 4.3).

Problems to be Solved by the Invention When the DPCM encoding unit is configured with a digital circuit, high-order processing requires a large number of calculations, so care must be taken against local overflow in the calculation circuit.

Furthermore, when there is an overload, that is, a large change in the input, it is necessary to prevent the output from overflowing in the adder circuit due to a large difference value from the predicted value. For this purpose, a pre-filter is installed to limit changes in the input.

On the other hand, since the DPCM decoder is a local circuit of the DPCM encoder, there is basically no overflow.

However, in reality, errors may occur during transmission from the DPCM encoder to the DPCM decoder, which may cause an overflow in the arithmetic circuit of the DPCM decoder.

A block diagram of a conventional DPCM decoder is shown in FIG. When error data is applied, the calculation output of the adder 2 overflows. At this time, go to Figure 6.

As shown in A2, in general, an audio signal quantized using two's complement representation jumps from a plus side peak to a minus side peak or vice versa, which causes large noise in the reproduced sound. Note that the solid line T is the actual output, and the dashed line is the output of the ideal calculation.

The present invention solves these conventional problems and provides an error protection circuit for a DPCM decoder that has a simple configuration and can suppress noise even if an overflow occurs due to a transmission error.

Means for Solving the Problems The error protection circuit for the DPCM decoder of the present invention is equipped with a circuit for detecting overflow and a configuration for replacing the adder output with a constant in accordance with this output and applying it to the predictor. Furthermore, several bits from the MSB side of the adder output are replaced with constants, and the remaining bits are directly applied to the predictor.

According to the above-described configuration, the present invention generates an overflow detection output when an error occurs and an overflow occurs, and this output is replaced with a constant of the upper limit value or lower limit value and applied to the predictor. The output is now clipped at the upper and lower limits, and there is no jump to the opposite polarity peak, which works to prevent large noise.

Embodiment FIG. 1 is a diagram showing an embodiment of an error protection circuit for a DPCM decoder according to the present invention. In FIG. 1, 1 is a dequantization ROM which dequantizes nonlinear data from a digital input terminal to restore the original word length. 2 is an adder, and 5 is an overflow detector, which has input terminals 51, 52 and 63, takes in the MSB data of two inputs and one output of adder 2, detects an overflow, and sends it to an output terminal 54. Output. A clip circuit 6 has an input terminal 61, a control input terminal 62, and an output terminal 63. Reference numeral 3 denotes a predictor, and a portion of its output is input to an adder 2, forming a prediction loop as a whole. 4 is a D/A converter which converts the digital output of the predictor 3 into an analog signal and outputs it to an analog output terminal.

The operation of the overflow detector will be explained.

Table 1 shows the amplitude of a 4-bit code expressed in two's complement.

Table 2 shows calculations for normal cases and overflow cases. In Table 2, a and s are normal cases, C8 is an overflow case, and d is an underflow case.

That is, the MSB of each input of the adder and the MSB of the output
Overflow can be detected from B.

This is shown in Table 3.

In Table 3, A and B are the respective MSs of the two inputs.
B and C is the MSB of the output.

Further, OVF and UDF indicate overflow and under 70-, respectively, and NOR indicates normality.

(Table 2) (Table 3) (1st formula) % formula% (2nd formula) Dl = UDF + NOR*lN1D2
= OVF + NOR*lN2D3 = O
VF + NOR*lN5Dn = OVF
+ NOR*INn therefore over 70 - detector 6
can be realized by a logic circuit based on the first logical formula.

Further, the clip circuit 6 can be realized by a logic circuit of the second formula. IN1 in the second formula. IN2゜I N n
is the data of the clip circuit input 61, Dl.

D2. ,, Dn is the data of the clip circuit output 63 +7+ In this way, the detection output 64 is applied to the clip circuit 6, the output data of the adder 2 is replaced with the upper and lower limit value data, and the predictor 3
and output to the analog output terminal through the D/A converter 4.

FIG. 3 shows the above operation as an analog output waveform, and even if there is an error and the limit value is reached, it can be clipped to prevent the generation of noise.

Next, other embodiments of the present invention will be explained.

FIG. 2 is a block diagram of an error protection circuit of a DPCM decoder according to another embodiment, and the same parts as in FIG. 1 are designated by the same numbers.

The difference from FIG. 1 is that a bypass 64 is provided in the clip circuit 6.

Generally, the operation word length is increased to reduce rounding errors, but in this embodiment, it is set to 24 pits.

The output word length to the D/A converter 4 is 16 bits.

Of the 24-bit output word length of the adder 2, the upper 8 bits are applied to the clip circuit input 61', and the remainder is applied to the bypass circuit 64.

The clipping circuit output 63' clipped according to the overflow condition is sent to the predictor 3 along with the data of the bypass 64.
Apply to.

With this configuration, the analog output waveform at the time of clipping is as shown in FIG. 4, which is slightly different from FIG. 3. This causes slight fluctuations in the clipped waveform. This means that only the upper 8 bits are clipped and the lower 16 bits are clipped.

This is because the amplitude remains the same, but its amplitude is 1 of the total.
/256, which is extremely small. Moreover, such clipping occurs when the signal amplitude is high and there are many errors, so the fluctuations are not noticeable.

In this embodiment, the data of the D/A converter 4 is obtained from the predictor 3, but it may also be obtained from the adder 2.

Effects of the Invention As explained in detail above, the DPCM according to the present invention
According to the error protection circuit of the decoder, (3) noise can be suppressed even if there is a transmission error over 70-.

By limiting error protection to the main upper bits, the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an error protection circuit of a DPCM decoder in one embodiment of the present invention, FIG. 2 is a block diagram showing an error protection circuit of a DPCM decoder in another embodiment of the invention, and FIG. is an operational waveform diagram in one embodiment of the present invention, No. 4
This figure is an operating waveform diagram of another embodiment of the present invention, FIG. 5 is a block diagram of an error protection circuit of a conventional DPCM decoder, and FIG. 6 is an operating waveform diagram thereof. 1...Dequantization ROM, 2...Adder, 3...Predictor, 4...D/A converter, 5...・・Overflow detector, 6・・・・
Clip circuit, 51, 52゜53...Overflow detection input terminal, 54...Overflow detection output terminal, 61...Clinop circuit input terminal,
62...Clip circuit control input terminal, 63...
...Clip circuit output terminal, 64...Side route. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 J & Width Figure 4 Figure 5

Claims (2)

[Claims] (1) A circuit that includes a dequantization ROM, an adder, a predictor, and a D/A converter, and that detects an overflow from the two inputs of the adder and the output of the adder, and the output of the overflow detection circuit. DP characterized in that the adder output is replaced with a constant and applied to the predictor according to the
Error protection circuit for CM decoder. (2) Error protection of the DPCM decoder according to claim 1, characterized in that several bits from the MSB side of the adder output are replaced with constants and the remaining bits are directly applied to the predictor. circuit.