JPS61121618A - Digital integration detection decoding circuit - Google Patents

Abstract

PURPOSE:To decrease a bit error by providing a means excluding a prescribe width both ends and center in one bit from the integration range in a digital integration detecting and decoding circuit converting a signal into a split phase signal NRZ signal. CONSTITUTION:An edge detection circuit 3-1 outputs a pulse detecting the trailing point at the center in addition to the pulse detecting the leading point of a recovery clock. A count range setting circuit 8 excludes a signal from the integration range at both ends within a bit and for a jitter at the center. A pulse setting the count range is generated and given to an integration counter 2-1 and the integration count is applied during this range. The output of the integration counter 2-1 is inputted to an FF 9 and smoothed by an output edge detection pulse by the edge detection circuit 3-1 and an NRZ signal is outputted from the FF 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides 1B2B data transmission system in order to prevent loss of timing information due to continuous 0 or 1 of NRZ signal.
This invention relates to an improvement of a digital integral detection decoding circuit that uses a split phase signal, which is a type of code, and converts it into an NRZ signal on the receiving side.

In the above digital integral detection decoding circuit, when a split phase signal is decoded into an NRZ signal, it is desirable that the bit error rate is small even if there is jitter.

The waveform of the sprint phase signal is shown in Figure 3 (A
) As shown in (B), to indicate 1 of the NRZ signal, the first half of 1 bit is θ level and the second half is level, and to indicate 0 of NRZ signal, it is 1 bit.

The first half of the target is level 0, and the second half is level 0.

[Conventional technology]

Fig. 4 is a block diagram of a conventional digital integral detection/decoding circuit, Fig. 5 is a time %-) of the waveform of each part in Fig. 4, and (A) to (H) are a to h in Fig. 4. corresponds to the point.

In the figure, 1 is an exclusive OR circuit, 2 is an integral counter which is an up/down counter, 3 is an edge detection circuit, 4 is a detection interval setting circuit, and 5.6 is an FF.

Figure 5(A) shows a 1-bit, 1-cycle regenerated clock for regenerating a split phase signal generated from the master clock 7 into an NRZ signal, and the split phase signal (in this case, 1 bit, 1 cycle) shown in Figure 5(B). ) is input to the exclusive OR circuit 1, exclusive OR is taken, and the result shown in FIG. 5(C) is output and input to the integral counter 2.

The integral counter 2 receives an edge detection pulse shown in FIG. 5(D) generated by the edge detection circuit 3 upon detecting the rising edge of the reproduced clock, and is reset by this pulse. Also, when the input is level, the integral counter 2 counts down and the output increases toward the 10th level, and when the input is at the O level, the integral counter 2 counts down and the output increases toward the 1st level.

Jitter as shown by the arrow in Figure 5(B) may occur in the split phase signal, and due to this jitter,
The output of the exclusive OR circuit 1 indicated by diagonal lines in FIG. 5(C) may become O level.

Therefore, the integral counter 2 counts down, and the level of the output fluctuates as shown in FIG. 5(E). In this case, if the shifter of the split phase signal is large, the period of 0 level of the output of the exclusive OR circuit l shown in FIG. What should be 10th level may become 1st level, and if the level is determined as level or O at the boundary point with the next bit and converted into an NRZ signal, many bit errors will occur.

In order to reduce this bit error, conventionally, the width of the shifter in the direction of the own bit from the boundary point with the next bit is assumed, and the pulse shown in FIG. is generated, inputs to FF5, hits the output from integral counter 2, and from the output of FF5, the signal shown in Fig. 5 (G
), input it to FF6, hit this input pulse at the rising point of the regenerated clock, and output the signal converted to NRZ shown in Figure 5 (H) from the output of FF6. There is.

[Problem that the invention seeks to solve]

However, in the conventional circuit, the leading edge and center of the bit where jitter occurs are also included in the integration range, so when the jitter in this range becomes large, the output of the integration counter 2 at the pulse point shown in FIG. 5(F) becomes There is a problem that the bit error rate deteriorates. Note that the same applies when the input signal is 0, although the sign is reversed.

[Means for solving problems]

The above problem is solved by the digital integration detection/decoding circuit of the present invention, which is provided with means for excluding predetermined widths at both ends and the center of one bit from the integration range.

[Effect]

According to the present invention, the width of the shifter that normally occurs at both ends and the center of one bit is assumed, and this width is excluded from the integration range, so even if the jitter is large, the level of the output of the integration counter is There is almost no reversal, and the bit error rate can be made very small.

〔Example〕

FIG. 1 is a block diagram of a digital integral detection/decoding circuit according to an embodiment of the present invention. FIG. 2 is a time chart of the waveforms of each part in FIG. - Corresponds to 1 point.

In the figure, 2-1 is an integral counter, 3-1 is an edge detection circuit,
7 is a count start bit setting circuit, 8 is a count range setting circuit, and 9 is an FF, and the same reference numerals indicate the same functions throughout the drawings.

The major difference between Fig. 1 and Fig. 3 is that the edge detection circuit 3-1 detects not only the pulse detected at the rising point of the recovered clock shown in Fig. 2 (CD), but also the falling point in the center. The pulse shown in FIG. 2(E) is also outputted, and this is outputted by the count start bit setting circuit 7 as shown in FIG. 2(B).
) is assumed to be the jitter width in the right direction of the arrow shown in FIG.
Assuming the jitter width in the left direction of the arrow in B),
As shown in Figure 2, a pulse is created to set the count range (counts between levels), excluding the width of the jitter at both ends and the center within one bit from the integration range, and is applied to the integration counter 2-1. This is the point where integral counting is performed during the range.

Therefore, the integral counter 2-1 counts during the level shown in FIG. 2 (C,), stops counting during the O level, and holds the previous value. This output rarely reverses and becomes one level.

The output of the integral counter 2-1 shown in FIG. 2 (H) is input to the FF 9, and is detected by the output of the edge detection circuit 3-1 shown in FIG. 2 (D). Takare, F.
An NRZ signal as shown in FIG. 2 (1) is output from F9.

Therefore, the bit error rate can be made very small and greatly improved.

〔Effect of the invention〕

As explained in detail above, according to the present invention, when decoding a sprint phase signal into an NRZ signal, even if the width of the shifter is large, the bit error rate can be made very small and can be significantly improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a digital integral detection/decoding circuit according to an embodiment of the present invention, Fig. 2 is a time chart of the waveforms of each part in Fig. 1, and Fig. 3 is a waveform corresponding to the NRZ signal of the split phase signal. FIG. 4 is a block diagram of a conventional digital integral detection/decoding circuit, and FIG. 5 is a time sheet of waveforms of various parts in FIG. 4. In the figure, 1 is an exclusive OR circuit, 2.2-1 is an integral counter, 3.3-1 is an edge detection circuit, 4 is a detection interval setting circuit, and 5 and 6.9 are FFs. 7 indicates a count start bit setting circuit, and 8 indicates a count range setting circuit.

Claims (1)

[Claims] A digital integral detecting and decoding circuit for converting a split phase signal into an NRZ signal, characterized in that the digital integral detecting and decoding circuit is provided with means for excluding predetermined widths at both ends and the center of one bit from an integral range.