JPS61121612A - Latch circuit - Google Patents

Abstract

PURPOSE:To prevent the software error due to a spike electromotive force caused by irradiation of an alpha ray by inserting a low pass filter consisting of a resistor and a capacitance to a feedback loop in a latch circuit having plural logical gate circuits and the feedback loop feeding back an output of at least a logical gate circuit to an input of the other logical gate. CONSTITUTION:Suppose that a data is stored in the state that an output Q is at a high level and an output Q' is at a low level and a negative noise pulse is caused to, a node A, by alpha ray irradiation in this state. The noise pulse is fed to a base of a transistor (TR) T6 via a TR T14 to cut off temporarily the TR T6 so as to generate a positive noise pulse to a node B. When a low pass filter LPF is inserted between an emitter of the TR T16 and the base of a TR T2 in this case, the noise pulse caused at the node B is not transmitted to the base of the TR T2 so as to prevent the inversion of a stored data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a latch circuit, and more particularly to a latch circuit in which a low-pass filter is inserted in a single fiber pack loop in order to cope with a shift error caused by α-ray irradiation or the like.

(Conventional technology) FIG. 5 shows an example of a conventional latch circuit.

There are three latch circuits in the figure (DNOI' -) G 1
, G2°G3. The respective outputs of NOR gates G1 and G2 are fed back to the input of the other N0Rf-1. Input data D is input to each input of NOR gate G3.
T and a clock/4' pulse CI,K are applied, and the N0Rf gate G3O output is connected to the input of the N0Rf gate GI. Further, an inverted clock/4 pulse CLK is applied to the input of the NOI''-to G2.

In the circuit of FIG. 5, as shown in FIG. 6, if the input data DT is at a low level when the clock signal CLK changes to a low level, the output of the NOR gate G3 becomes a high level. At this time, assuming that the output Q of the N0Rf gate Gl is initially at a high level, the output Q changes to a low level. Therefore, the inverted clock pulse d
1 changes from high level to low level, the two inputs of NOR G2 both become low level, and the output ζ changes to high level. As a result, one input terminal of NOR gate G1 is kept at high level, and the output Q is kept at low level even after the output of NOR gate G3 changes from high level to low level. Furthermore, if the input data DT is at a high level at the time when the clock pulse CLK changes from a high level to a low level, the output of NOR G3 is held at a low level. At this time, when the inverted clock pulse CLK changes from low level to high level, the output level of N0R gate G2 becomes low level, and accordingly, NOR
The output Q of gate G1 changes to high level. Even after the inverted clock/4 pulse CLK changes from a high level to a low level, one input of N0Rr-)G2 is kept at a high level by the output Q, so the output Q is kept at a low level. .

By the way, even in integrated circuit devices using latch circuits such as those mentioned above, due to the need to improve the degree of integration, the main elements have recently been miniaturized, the amplitude of internal signals has been reduced, and the power consumption of the circuit has been reduced. .

Along with this, soft errors due to alpha rays emitted from radioactive substances contained in the ceramic of the /4 cage member have become a problem. In other words, in conventional latch circuits, no special measures were taken against this soft error, so there was an inconvenience in that the data stored in the latch circuit was destroyed by the snow-like electromotive force caused by alpha ray irradiation. (Problems to be solved by the invention) In view of the problems with the conventional type described above, the present invention prevents soft errors caused by spike-like electromotive force caused by α-ray irradiation and improves the reliability of the latch circuit. The purpose is to

(Means for Solving the Problems) In the present invention, a plurality of logic gate circuits and a feedback circuit that feeds back the output of at least one logic gate circuit among these logic gate circuits to the input of another logic gate circuit are provided. In a latch circuit having a loop, a configuration is used in which a low-pass filter formed by a resistor, a capacitor, etc. is inserted into the feedback loop.

(Function) By using the above-mentioned means, the spike-like electromotive force generated by α-ray irradiation etc. is prevented from being fed back to the input side via the feedback loop, and therefore the latch circuit is Memory contents are prevented from being destroyed.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a latch circuit according to an embodiment of the present invention.
Goo) A low-pass filter L is connected to the feedback circuit connected to the input of Gl.
This is with a PF inserted. The low-pass filter LPF is composed of, for example, a resistor R inserted in series in a feedback circuit and a distributed capacitance C provided between this resistor 8 and ground. Alternatively, the low-pass filter LPF may be constituted by the resistor R and a voltage capacitor present in each part of the feedback circuit, or a capacitor may be connected between the feedback circuit and ground. The other parts are the same as the circuit of FIG. 5 and are designated by the same reference numerals. The operation of the latch circuit in Fig. 1 is the same as that in Fig. 5 described above, but the latch circuit operates because the snow-like electromotive force caused by α-ray irradiation is blocked by the low-pass filter LPF inserted in the feedback circuit. Destruction of the memory contents is prevented.

FIG. 2 shows a detailed circuit configuration of the latch circuit of FIG. 1. In FIG. 2, transistor TI.

T2. T3. T4 and resistors R1, R2, R3 are ECL
This is what constitutes the NOR gate of the type shown in Figure 1).
Corresponds to Gl. Transistors T5, T6°T7.
T8 and resistors R5 and R6 are EC corresponding to gate G2
Configures an L-type N0Re-to. Furthermore, the transistor T
9, TIO, T11, T12 and resistors R7, R8
, R9 is an ECI corresponding to gate G3, type NOR type P-
) is connected to one input of gate G1, ie to the pace of transistor T1, via an emitter follower constituted by transistor T13 and resistor RIOK. The output of the ff-to-G1 is taken out as an output Q through an emitter follower constituted by a transistor T15 and a resistor R12, and is taken out as an output Q through an emitter follower constituted by a transistor T14 and a resistor R11 to one of the f-to-G2. It is connected to the input or pace of transistor T6. In addition, the output of the gate G2 is taken out as an output Q via an emitter follower composed of a transistor T17 and a resistor R14, and is also taken out as an output Q via an emitter follower composed of a transistor T16 and a resistor R13.
one input, namely the pace of transistor T2. However, a low-pass filter LPF constituted by a resistor R and a capacitor C is inserted in the feedback circuit extending from the emitter of the transistor T16 to the transistor 2 pace.

In the circuit of FIG. 2, input data DT and clock pulse CLK are applied to each input of the NOR gate 3, that is, the pace of transistors T9 and TIO. Each of these input signals is low 1.
In the case of Novell, transistors 9 and TIO are both cut off, and transistor Tll is turned on. Therefore N connected to the transistor T130 pace
The output of 0Rf gate G3 becomes high 1 novel. On the other hand, when at least one of the input data DT i or the clock pulse CLK is at a high level, the transistor T9t or 710 is turned on, υ, and the transistor Tll
is turned off. Therefore, the output of NOR/gate G3 becomes a low 1 novel. other N0Rr-)Gl and G
2 operates on a similar principle. And each NO like this
R gate G1. G2. G3 performs the same operation as the latch circuit of FIG. 5 described above.

By the way, in the circuit shown in FIG. 2, it is assumed that data is held in a state where the output Q is at a high level and the output σ is at a low level, for example. At this time, NOR? -) In the transistor G1, both 1 and T2 are cut off, and node A is at a high level. Also, the transistor T6 of the NOR gate G2 is turned on, and the node B
is kept at a low level. In this state, it is assumed that a noise pulse of negative polarity is generated, for example, at node A due to α-ray irradiation. This noise/mother pulse is the transistor T14'
is applied to the pace of transistor T6 through the transistor T6, temporarily cutting off the transistor T6 and generating a positive noise pulse at node B. At this time.

If the emitter of transistor T16 and transistor T2
Assuming that a low-pass filter M is not inserted between the paces of , the noise pulse is fed back to the pace of 2 by the transistor of the NOR gate 11 via the transistor T16, and the potential of the node person is still lowered to a low level. It works like this. As a result, the data stored in the latch circuit is destroyed. On the other hand, if the low-pass filter L is connected between the emitter of transistor T16 and the base of transistor T2,
If PF is inserted, the noise pulse generated at node B will not be transmitted to the transistor T2, and the above-mentioned inversion of stored data will be prevented. Note that it is preferable that the low-pass filter LPF be inserted in the final stage feedback circuit when viewed from the terminal into which the input data DT is input. By inserting the signal at such a position, for example, each signal does not pass through the low-pass filter LPF until the output Q and each other are output according to the levels of the input data DT and the clock terminal CLK. After the occurrence of the problem, is it first passed through the low-pass filter LPF? −) Since each output Q
and high-speed operation can be performed without suffering transmission delay.

FIG. 3 shows a latch circuit according to another embodiment of the invention. The circuit in the figure consists of three OR gates G4, G5. G6
and one AND gate G7. The positive outputs of OR gates G4 and G5 are AND) la-to G7
1 of the output of AND gate G7
One is 1 of 0R)f-toG5 via the low-pass filter LPF.
It is fed back to two inputs. Also, each 0R) Ia-G
The inverted outputs of G4 and G5 are wired ORed in OR gate G6 to generate an inverted output. The affirmative output Q is taken from the other output terminal of the connector G7. AMDI'-) G 7 can also be configured by a wired piece circuit.

The operation of the latch circuit in FIG. 3 is the same as that of each latch circuit described above. For example, if the input data DT is low level when the clock pulse CLK changes from high level to low level, the output Q is low level. Changes to The way this low level comes out is from the MΦ gate G7 to the low pass filter LPF.
is fed back to the input of the OR gate G5 through the inverted clock pulse CLK, and the output Q of the OR gate G5 is kept at a low level even after the inverted clock pulse CLK becomes a low level. At this time, the output of ORG6 is held at the output threshold level. Also, Clockz 9rus C
If the input data DT is at a high level when LK changes from high level to low level, the output of 0R gate G4 becomes high level. At this point, the inverted clock/4 rus ct
When gt changes from low level to high level, 0Rr-toG5
The output of ANDf gate G7 becomes high level.

Therefore, the output Q of the latch circuit is not at a high level, and this high level output is ORed via the low pass filter LPF.
(G) It is fed back to the input of G5 and data is held.

FIG. 4 shows a specific circuit configuration of the latch circuit shown in FIG. 3. In FIG. 4, transistors T18°T19,
T20, T21, diode D1, resistor R15, R1
6, R17 constitutes the KCL type ORI'-) and corresponds to G4 in FIG. Also, transistor T2
2, T23, T24, T25, and resistor R18
, R19 constitutes an ECL type OR gate, and ff in FIG.
-) Equivalent to G5. In addition, the transistor T24
The collector of the transistor T24 is connected to the collector of the transistor T24 to form a wired gate, which corresponds to the gate G7 in FIG. Furthermore, transistor T28. T29
and resistor R22 constitute a wired 0R gate and the third
This corresponds to ff-G6 in the figure. Note that the emitter follower constituted by the transistor T26 and the resistor R20, the transistor T27 and the resistor R21
The emitter followers constructed by the above are used as a feedback circuit and an output buffer circuit, respectively.

The operation of the circuit shown in FIG. 4 is the same as that described for the circuit shown in FIG. 3, so a description thereof will be omitted.

(Effects of the Invention) As described above, according to the present invention, due to the extremely simple circuit configuration, the S/-P current electromotive force generated by α-ray irradiation is not fed back to the input side. It becomes possible to accurately prevent soft errors caused by radiation, alpha rays, etc. Further, since the delay time of the output signal of the latch circuit does not increase, a high-speed latch circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an outline of a latch circuit according to one embodiment of the present invention, FIG. 2 is an electric circuit diagram showing details of the circuit in FIG. 1, and FIG. 3 is another embodiment of the present invention. 4 is an electrical circuit diagram showing details of the circuit in FIG. 3, FIG. 5 is a block circuit diagram showing an outline of a conventional latch circuit, and FIG. Fifth
FIG. 3 is a waveform diagram for explaining the operation of the circuit shown in the figure. Gl, G2, G3 two NOR sheets
, G4. G5゜G6: OR gate, G7: AN
D? R: resistance, C: capacitance, LPF: low-pass filter, Tl, T2,... T29: ) transistor, R1, R2,..., R2
2: Resistor, Dl: Diode. (,2LPF -)2Figure 3Figure 4

Claims (1)

[Claims] 1. A plurality of logic gate circuits, a feedback loop circuit formed by feeding back the output of at least one logic gate circuit to the input of another logic gate circuit, and a feedback loop circuit inserted into the feedback loop circuit. A latch circuit comprising a low-pass filter. 2. The plurality of logic gate circuits include two NOR gate circuits, and the output of the first NOR gate circuit is the output of the second NOR gate circuit.
The second NOR gate circuit output is fed back to the input of the first NOR gate circuit, and a low-pass filter is inserted in at least one of the feedback circuits. The latch circuit described. 3. The plurality of logic gate circuits include two OR gate circuits and one AND gate circuit, and the first and second O gate circuits include two OR gate circuits and one AND gate circuit.
The output of the R gate circuit is input to the AND gate circuit, and the A
The output of the ND gate circuit is fed back to the input of the first or second OR gate circuit to form a feedback circuit, and a low-pass filter is inserted in the feedback circuit.
The latch circuit described in section. 4. The latch circuit according to any one of claims 1 to 3, wherein the low-pass filter is an integrating circuit including a resistor and a capacitor.