JPS61120461A - Cmos semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a structure of a CMO8 semiconductor device capable of reducing lateral resistance and preventing latch-up, and a method of manufacturing the same. 0MO to reduce lateral resistance in the well region and reduce latch-up
8 structure.

(2) Background of the Technology A common problem resulting from OMO8 structures is their vulnerability to an undesirable conduction mechanism known as latch-up. Latch-up is a condition in which a large current flows between VDD and vSS, resulting in the inability of an integrated circuit (IC) to function or even destruction of the IC. In particular, CMO8 integrated circuits typically contain a parasitic PNPN structure that causes an undesirable latch-up condition through SCR operation where one of the junctions in the channel is turned on by an applied forward bias. It is believed that this is the case. Even after the signal that applied the forward bias is removed, the on state continues, causing destruction of the device due to excessive current. Parasitic n
The current gain of the pn and pnpt' transistors is an important parameter in control to avoid latch-up. If the product of the current gains of the two transistors is greater than 1, the device latches. Several techniques have been used for the low current gain of the two devices, including longer gold doping and neutron irradiation to shorten the minority carrier lifetime. Methods for eliminating these and other latch-ups are described in IEEE Bulletin of Nuclear Science, December 1979, Volume MS-26, 16.6.
(I E EE Transactions 1nNu
clear 5science,'Vo1. N.S.
-26,166.

Dec, 1979), pp. 5056-5058, by Okoa et al.
Latch-up control in CMO8 integrated circuit J (La
tchup Control in CMO8Inte
rated C1rcuits).

Those techniques are difficult to control and also cause deleterious effects (eg, excessive leakage) on device operation.

(3) Structure of the Invention The structure of the CMO8 semiconductor of the present invention has an n-type well region formed in a p-type substrate, and uses proton irradiation to form an n-type impurity at a predetermined position in the n-type well region. Increasing the concentration reduces the n-type lateral resistance, thereby suppressing latch-up associated with the resistance of the n-well region.

(4) Embodiments of the Invention As mentioned above, a common problem associated with CMOS structures is their vulnerability to latch-up. General twin well C
In FIG. 1, which shows the MO8 structure, a parasitic bipolar device formed by the CMO8 manufacturing process is shown.

The structure of FIG. 1, which is formed by conventional techniques, uses a p-type substrate 10 on which a p-type epitaxial layer 12 is grown. Note that a gate oxide layer is subsequently grown on the p-type epitaxial layer 12, and a gate region is formed. However, these areas are not shown in FIGS. 1-5 for simplicity. Using mask processing and diffusion processing,
P-type well 14 and n-type well 16 are formed within p-type epitaxial layer 12 . Shallow n-type diffusion terminals 18 and 20 are then formed in p-well 14, and similarly p-type terminals 22 and 24 are formed in n-well 16. The p-swelling diffusion layer 26 and the n-swelling diffusion layer 28 are connected to power sources (VSS and VSS).
DD) and the device concerned. A full description of the twin well formation process is provided in U.S. Pat. No. 4,435,89.
It's in issue 6.

Although the structure shown in FIG. 1 consists of a number of parasitic bipolar devices, only two transistors of each polarity are shown for clarity. 1st
Referring to the figure, pnp transistor 30 is located in region 24,
The region 24 is formed between the n-type well 16 and the p-type well 14, and the region 24 is the emitter of the transistor 30 and the n-type well 16.
is the base, and the p-type well 14 (the same applies to the p-type epitaxial layer 12 and the substrate 10) is the collector. Additionally, a lateral resistor 32 is formed between transistor 30 and n-type contact diffusion region 28 . Similarly, the second pn
pl' transistor 34 and resistor 36 are connected to p-type terminal 22 (emitter), n-type well 16 (base) and p-type well 14 (
is formed between the collector and the collector. A pair of lateral npn transistors are formed located within p-well 14. The first npn transistor 40 has an n-type region 18, p
The transistor 40 is formed of a type well 14 and an n-type well 16, with the region 18 forming the emitter of the transistor 40, the p-type well 14 forming the base, and the n-type well 16 forming the collector. Resistor 42 is connected to the base of transistor 400 (p-well 14
) and the p-type region 2G. n-type region 2
0, the p-type well 14 and the n-type well 16 are each np
Serving as the emitter, base, and collector of the n-parasitic transistor 44, a resistor 46 is formed between the base of the transistor 44 (p-type well 14) and the p-type region 26. The collector of each of the bipolar transistors feeds the base of each transistor and the thyristor (
p-n-p-n).

Referring to FIG. 2, pnp transistors 30 and 34 (of FIG. 1) are simply T2, and resistors 32 and 36 are R
Shown as N. Similarly, npn transistor 4
0 and 46 (Fig. 1) are T1, also resistors 42 and 46h
RP to facilitate the explanation of thyristor operation that results in latch-up. In particular, if the thyristor is properly biased, the collector current of pnp transistor T2 will be lower than that of npn transistor Tl.
The base current to f#@L is the opposite of a positive feedback device.

Therefore, current can continue to flow between the positive and negative terminals of the transistor, resulting in what is called latch-up. In particular, if the voltage at the terminal related to ■SS temporarily becomes lower than the VSS potential by about 0.7V (for example, due to pseudo-spike noise caused by electrostatic discharge), n+ regions 18 and 20 (npn transistor The emitter of Tl supplies electrons to the p-well 14 (base of transistor T1), which electrons reach the n-well 16 (collector of transistor Tl) where they flow out of the positive terminal 28. At this time, if the flow of electrons is sufficiently large and the resistance between the connection end 28 to VDD and the p+ regions 22 and 24 is sufficient, then ■R drop will occur, and the p+ region 22 and The potential of the n-type well 16 below 24 drops by about 0.7V. This voltage drop is caused by the p-type regions 22 and 24 (pn
p the emitter of transistor T2) to the spiral well 16 (
The holes are released to the base of the transistor T2. The drawn hole reaches the p-well 14 (collector of transistor T2) and flows out from the vSS terminal 26. If sufficient hole current exists in the p-type well 14 and the p-type region 26 and n
If there is sufficient resistance between the n+ region 18 and the p-well 14, an IR drop will occur and electrons will be injected from the n+ region 18 into the p-well 14. This electron current is added to the initial electron current to promote positive feedback of the pnp and npn transistors Tl and T2. This phenomenon leads to latch-up conditions.

What makes the latch-up phenomenon even more troublesome is
Current to the 0M08 circuit is interrupted (i.e. VDD or v
The fact is that unless either SS is disconnected, the large latch-up current will naturally continue after the initial fault is removed.

An effective technique for suppressing latch-up is to reduce the resistance, shown as RN and RP in FIG. 2, that shunts the emitter-base connection of the parasitic bipolar transistor. If these shunt resistors are small enough, the large IR drop mentioned above will not be caused by them and the emitter-base connection will be forward biased.

And the device is not latched. Therefore, according to the present invention, the shunt resistor RN provided in the n-type well 16
Disclosed is a method for reducing. As discussed in more detail below, one advantage of the present technique is that it can be performed immediately prior to the final metallization of the device and therefore does not conflict with conventional processing techniques.

3-5 illustrate the process steps necessary to reduce the resistance of n-well 16 to prevent latch-up in accordance with the present invention. Although FIGS. 3-5 depict a dual-well CMO8 structure, the invention is equally applicable to single-well devices, and the dual-well structure is used for illustrative purposes only. be. Referring to FIG. 3, the starting point for the process of the present invention is, for example, a twin-well CMO3 structure throughout all manufacturing steps except for the final metallization. Figure 3 shows its typical structure.
It has a p+ substrate 10 and a p-type orbital layer 12 covering the substrate 10. The p-type well 14 and the n-type well 16 form a double well structure, and the n-swelled diffusion layers 18 and 20
and p-swelled diffusion layers 22 and 24 become source or drain regions within p-type well 14 and n-type well 16, respectively.

As mentioned above, p-swelled diffusion layer 26 and n-swelled diffusion layer 28 are used to provide power supply voltages vSS and VDD to the device. A patterned oxide layer 5o has been deposited on top of the above-described structure, and the windows in this layer 50 are for forming the final metal connections.

As stated above, the present invention is directed to a method of eliminating latch-up by reducing the lateral resistance of an n-well. The resistance is reduced in accordance with the present invention by proton bombarding the n-well 16 with high energy to form a high concentration n-type implant region within the n-type valve door. This process is illustrated in FIG.

In order to inject protons only into the n-well, the n-well 16 (
A patterned mask layer 52 is deposited to cover all other areas except the N-wells and all other n-wells in the substrate. Then proton injection is carried out,
This includes hydrogen ions (or divalent helium ions Hc
++) is used as the injection beam. It is well known that the depth of ion implantation is determined by controlling the implant energy. Figure 6 shows the 1981 Electronic Devices Conference J (the 1981 Intern
ationalElectron Devices M
``Full Isolation Technology Using Porous Silicon Oxide and Its Application to LSI J'' written by Imai et al. on pages 376 to 379 of
logy by Porous QxidizedSi
licon and its Application
s to LS I s).

Same figure! 1 is a graph showing the relationship between implant depth and proton donor concentration for various implant energies.

For example, at an implantation energy of 15oKeV, the dose I
When hydrogen ions are implanted at 10I5cm-2, I
A donor concentration of 10" cm is formed at a depth of approximately 1.4 μm. According to the present invention, hydrogen ions are
It must be implanted deeper than the shaped regions 22 and 24.

Therefore, the location of the n-type region can be controlled using a graph similar to that of FIG. 6, thereby determining the appropriate implant energy and dose to provide the desired implant location.

The structure formed by the present invention is shown in diagram g5. In this figure, the mask layer 52 has been removed. As shown in the figure, proton bombardment by hydrogen ions (! or helium ions) moves the n+ region 54, also called a regressive n-well, into the n-well 1.
6 below p-type regions 22 and 24. n+
The dopant concentration in region 54 is, for example, I x 1017
By increasing crrV3, the lateral resistance RN
is significantly reduced.

Therefore, the IR drop due to the RN is reduced and the device does not latch. Furthermore, the presence of n+ region 54 damages the base region of the vertical pnp transistor formed between p-type region 24, n-type well 16, and p-type epitaxial layer 12. Damage to the base of this parasitic transistor reduces the gain of the vertical transistor. This decrease in gain also helps prevent latch-up.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a typical dual-well CMO8 showing the location of the parasitic bipolar transistors forming a latch-up pnpn operation, and FIG. 2 shows the interconnections of the parasitic bipolar transistors shown in FIG. FIGS. 3 to 4C5 are diagrams showing the process of forming a regressed n+ region according to the present invention, and FIG. 6 is a diagram showing typical depth dependence of proton donor concentration. [Explanation of symbols of main parts] 10... Semiconductor substrate 14... P type Well region 16......N-type well region 54...N+ region FIG, 2 FIG, 4

Claims (1)

[Claims] 1. Having n-type well regions (for example, 16) on its surface in which a MOS transistor is formed, each of the well regions having a lateral resistance determined by processing conditions. and another n-type semiconductor substrate formed in a part of the n-type well region to reduce the lateral resistance of the n-type well and prevent latch-up in the MOS transistor.
A semiconductor device characterized in that it has a shaped region (for example, 54). 2. The semiconductor device according to claim 1, wherein the semiconductor substrate surface further has a p-type well region provided to pair with the n-type well region. 3. A method for manufacturing a semiconductor device in which latch-up is prevented, including the steps of: (a) forming a semiconductor substrate having a p-type well region on the surface, and the well region having a predetermined lateral resistance; (b) selectively bombarding a portion of the semiconductor substrate having the n-well region with protons to form a predetermined lateral portion of the n-well region along a predetermined lateral portion of the n-well region; A method of manufacturing a semiconductor device, comprising the step of forming an n^+ region to reduce directional resistance and prevent latch-up. 4. The method of manufacturing a semiconductor device according to claim 3, wherein hydrogen ions are used as a source of proton bombardment in the step (b). 5. The method of manufacturing a semiconductor device according to claim 3, wherein divalent helium ions are used as a source of proton bombardment in the step (b).