JPS61120448A - High-withstanding-voltage semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the concentration of the surface electric field at the interface of an oxide film and to obtain a compact, high withstanding voltage IC, by bending the edge of a depletion layer on the low concentration side to the side of an IC substrate in the IC having a planar structure, and forming the thick oxide film on the depletion layer region. CONSTITUTION:When the potential of a wiring metal 1 on the high concentration side at a P-N junction 5 is lower than that of a wiring 2 on the lower concentration side, a depletion layer 6 is yielded. Before the depletion layer 6 reaches a planar surface, the layer 6 reaches an oxide film 4, which is formed so as to form an obtuse angle with the depletion layer 6, at the lower side from the surface and at the side of a substrate 8. The layer 6 is bent to the substrate 8 at the interface of the film 4. The surface electric field of the oxide film interface 4 is alleviated. The oxide film 4 is formed so as to form an acute angle with a surface 7 on the upper side of the surface 7. Therefore, the distance between the substrate 8 and the wiring metal 1 becomes large. The concentration of the electric field at the tip of the wiring 1 is alleviated by only extending the wiring 1 to the region of the oxide film 4. In this constitution, the high withstanding voltage IC with small sizes can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a semiconductor integrated circuit which has a planar structure and is particularly excellent in achieving high withstand voltage.

[Conventional technology]

A conventional high voltage semiconductor integrated circuit having a planar structure will be explained with reference to FIG. In the following explanation, a case will be explained in which a P expansion diffusion layer is formed on an N-type semiconductor substrate. The same applies to the case where an N-type wave diffusion layer is formed on a P-type semiconductor substrate.

In FIG. 2, 1 and 2 are wiring metals, 3 is an oxide film, 5 is a PN junction, 6 and 9 are depletion layer regions, 7 is a planar surface,
8 shows a part of the semiconductor integrated circuit board. Here, the same components as in FIG. 1 are indicated by the same symbols as in FIG. 2.

In FIG. 2, when the potential Vp of the high-concentration wiring metal 1 of the PN junction is lower than the potential vN of the low-concentration wiring metal 2 of the PN junction, the PN junction 5 is in a reverse bias state.
A depletion layer region 6 as shown in the figure is generated. An electric field is concentrated at the point where this depletion layer region 6 reaches the planar surface 7,
The breakdown voltage of the PN junction is limited.

In order to prevent this, as shown in FIG. 2, the wiring metal 1 on the high concentration side of the PN junction is extended to cover the PN junction 5 and the depletion layer region 6, and a new depletion layer region 9t- is formed. , the structure is such that electric field concentration on the planar surface 7 can be relaxed and the breakdown voltage of the PN junction can be increased.

This is commonly referred to as the field plate effect.

[Problem that the invention seeks to solve]

In the conventional structure described above, the wiring metal on the high concentration side of the PN junction is extended to cover the PN junction, and its size must be increased in proportion to the reverse voltage applied to the PN junction. The distance between the high-concentration wiring metal of the junction and the low-concentration wiring metal of the PN junction requires a dimension determined by the design standards of semiconductor integrated circuits, which naturally increases the dimensions of high-voltage semiconductor integrated circuits and increases the chip size. However, this method has the disadvantage that it leads to an increase in the yield rate and a decrease in the yield.

[Means for solving problems]

The present invention provides a high breakdown voltage semiconductor integrated circuit having a planar structure, in which a low concentration semiconductor region including a low concentration semiconductor region including the depletion layer region is covered with an oxide film before the low concentration side depletion layer region reaches the planar surface. Then, the oxide film and the depletion layer region are replaced so that they form an obtuse angle, and the oxide film is formed above the planar surface to form an acute angle with the planar surface, and the wiring metal on the high concentration side of the PN junction is placed on the planar surface. This is a high-voltage semiconductor integrated circuit characterized by extending to an oxide film region that forms an acute angle with the oxide film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a structural diagram of a high voltage semiconductor integrated circuit having a planar structure showing an embodiment of the present invention.

In Figure 1, 1.2 is a wiring metal, 3 and 4 are oxide films,
5 is a PN junction, 6 is a depletion layer region, 7 is a planar surface,
8 shows a part of the semiconductor integrated circuit board.

In FIG. 1, when the potential Vp of the high-concentration wiring metal 1 of the PN junction is lower than the potential VN of the low-concentration wiring metal 2 of the PN junction, the PN junction 5 is in a reverse bias state.
A depletion layer region 6 as shown in the figure is generated.

Before reaching the planar surface 7, the depletion layer region 6 reaches an oxide film 4 formed below the planar surface 7 and on the semiconductor integrated circuit substrate 8 side so as to form an obtuse angle with the depletion layer region 6.

Due to the oxide film 4 formed to form an obtuse angle with the depletion layer region 6, the depletion layer region 6 is bent toward the semiconductor integrated circuit substrate 8 at the interface of the oxide film 4, as shown in the figure. This is considered to be a kind of bevel structure, and the surface electric field at the interface of the oxide film 4 is relaxed.

Further, since the oxide film 4 is formed above the planar surface 7 and on the semiconductor integrated circuit surface side to form an acute angle with the planar surface 7, the semiconductor integrated circuit substrate 8 and the PN
The distance between the junction and the wiring metal 1 on the high concentration side increases, and by simply extending the wiring metal 1 on the high concentration side to the area of the oxide film 4 formed at an acute angle with the planar surface 7, the wiring metal 1 on the high concentration side Electric field concentration at the tip of the wiring metal 1 is alleviated.

〔Effect of the invention〕

As explained above, with the structure according to the present invention, the low concentration side depletion layer region has a curve 9 on the semiconductor integrated circuit substrate side, and the oxide film on the depletion layer region is also formed thickly.
Surface electric field concentration at the oxide film interface can be prevented.

As a result, in order to form a high voltage semiconductor integrated circuit,
In order to alleviate the concentration of electric field on the planar surface, the wiring metal on the high concentration side of the PN junction does not need to be made large enough to have a field plate effect, and a high breakdown voltage semiconductor integrated circuit can be obtained with a small size, reducing the chip size. It has the effect of reducing size and improving yield.

[Brief explanation of drawings]

Fig. 1 is a structural diagram of a high voltage semiconductor integrated circuit according to the present invention;
The figure is a structural diagram of a conventional high voltage semiconductor integrated circuit. 1.2... Wiring metal, 3,4... Oxide film, 5...
PN junction, 6.9... Depletion layer region, 7... Planar surface, 8... Partial patent applicant for semiconductor integrated circuit board NEC Corporation 6: Depletion layer region 7 Ni planar i; ζ1 Figure 2

Claims (1)

[Claims] (1) In a high voltage semiconductor integrated circuit having a planar structure, before the low concentration depletion layer region reaches the planar surface of the high voltage semiconductor integrated circuit, the low concentration semiconductor region including the depletion layer region is formed into an oxide film. , the oxide film and the depletion layer region are replaced so that they form an obtuse angle, and the oxide film is formed above the planar surface to form an acute angle with the planar surface, and the wiring metal on the high concentration side of the PN junction is formed with the planar surface. A high-voltage semiconductor integrated circuit characterized by an oxide film extending into an acute-angled region.