JPS61120430A - Method of sealing ic substrate - Google Patents

Method of sealing ic substrate

Info

Publication number
JPS61120430A
JPS61120430A JP24200684A JP24200684A JPS61120430A JP S61120430 A JPS61120430 A JP S61120430A JP 24200684 A JP24200684 A JP 24200684A JP 24200684 A JP24200684 A JP 24200684A JP S61120430 A JPS61120430 A JP S61120430A
Authority
JP
Japan
Prior art keywords
hole
substrate
holes
sealing
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24200684A
Other languages
Japanese (ja)
Inventor
Hirohisa Hino
裕久 日野
Masanobu Miyazaki
宮崎　政信
Taro Fukui
太郎 福井
Masaya Tsujimoto
雅哉 辻本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP24200684A priority Critical patent/JPS61120430A/en
Publication of JPS61120430A publication Critical patent/JPS61120430A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a rear-face electrode of an IC substrate from being covered with resin entering into through holes in the substrate, by closing up the entrances of the through holes on the surface of the substrate during the process of sealing the substrate with the resin. CONSTITUTION:A jig 9 is provided such that an IC substrate 1 having through holes 5 can be fixed thereon. Pins 10 having an approximately same diameter as the through holes 5 and the same height with the depth of the through holes 5 are mounted vertically on the jig 9 in the positions corresponding to the through holes in the substrate 1. The pins 10 are inserted into the through holes 5 so that resin is prevented from entering into the holes even if the viscosity of the resin is changed during the sealing with the resin 11. The holes 5 are thus closed up with the pins 10 until the resin is hardened. According to this method, the rear-face electrode of the substrate 1 is not covered with the resin and therefore no defect in continuity is produced.

Description

【発明の詳細な説明】 〔技術分野〕 この発明は、ＩＣの保護を行うためにエポキシ樹脂等の
半導体封止樹脂でＩＣを封止するＩＣ基板の封止法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an IC substrate sealing method for sealing an IC with a semiconductor sealing resin such as an epoxy resin in order to protect the IC.

〔背景技術〕[Background technology]

半導体の高集積化、高信頼性化の要求に伴って、半導体
のパッケージング方法も発展してきてい−る。半導体の
パッケージング方法の一つにチップキャリア方式がある
。チップキャリア方式は、セラミックなどの基板上にＩ
Ｃチップを装着し、金ワイヤーなどでＩＣチップと電極
を結ぶ方式である。その際、電極を基板の裏面にもって
（るよ、うにすると、各種のｖ４張り８Ｉ層板などに、
ハンダリフローによって、簡単にワイヤレスで取りつけ
ることができる。電極を基板の裏面にもってきて、表の
ＩＣチップと裏の電極を結ぶ方法として、最近では、ス
ルホールを基板に形成し、そのスルホールを通してＩＣ
チップと電極を結ぶ方法が主に用いられるようになって
いる。すなわち、第１図（ａ）および（ｂ）にみるよう
に、ＩＣ基板１表面のＩＣ。With the demand for higher integration and higher reliability of semiconductors, semiconductor packaging methods are also being developed. One of the semiconductor packaging methods is the chip carrier method. In the chip carrier method, I
In this method, a C chip is attached and the IC chip and electrodes are connected using gold wire or the like. At that time, if you put the electrode on the back side of the board,
Easy wireless installation using solder reflow. Recently, as a method of bringing the electrode to the back side of the substrate and connecting the front IC chip and the back electrode, a through hole is formed in the substrate and the IC chip is inserted through the through hole.
The method that connects the tip to the electrode is now mainly used. That is, as shown in FIGS. 1(a) and 1(b), an IC on the surface of an IC substrate 1.

チップ２は、金ワイヤ−３を介して、ＩＣ基板表面の導
体４に導通され、導体４はスルホール５に導かれている
。スルホール５の内面には、第２図の拡大図にみるよう
に、導体６がメッキされていて、ＩＣ基板表面の導体４
とＩＣ基板裏面の導体７が繋がれている。４体７は、Ｉ
Ｃ基板裏面の電極８に達し、ＩＣチップ２と電極８を電
気的に繋ぐようにする。このようにすると、ＩＣチップ
から電極までの距離が短くてすむため、ＩＣチップの信
頼性が向上する。The chip 2 is electrically connected to a conductor 4 on the surface of the IC board via a gold wire 3, and the conductor 4 is led to a through hole 5. The inner surface of the through hole 5 is plated with a conductor 6, as shown in the enlarged view of FIG.
and the conductor 7 on the back side of the IC board are connected. 4 bodies 7 is I
It reaches the electrode 8 on the back surface of the C substrate and electrically connects the IC chip 2 and the electrode 8. In this way, the distance from the IC chip to the electrode can be shortened, and the reliability of the IC chip is improved.

このようなＩＣ基板においては、ＩＣチップ、の保護を
行うため、エポキシ樹脂等の半導体封止樹脂で基板表面
を封止することが行われている。ところが、封止樹脂の
粘度が低かったり、流れ性が良すぎたりする場合には、
封止樹脂がスルホール内に流れ込み、さらミは、スルホ
ールを通って裏面に流れ出てしまい、裏面の電極が封止
樹脂により被覆され、絶縁されてしまうことが起こる。In such an IC substrate, in order to protect the IC chip, the surface of the substrate is sealed with a semiconductor sealing resin such as an epoxy resin. However, if the viscosity of the sealing resin is low or the flowability is too good,
The sealing resin flows into the through-hole, and the loose material flows out to the back side through the through-hole, and the electrode on the back side is covered with the sealing resin and becomes insulated.

また、スルホール内に封止樹脂が充垣されたままで、封
止４Ｍ脂の硬化を行うと、封止樹脂が硬化収縮する際に
、スルホール内の導体が切断される可能性がある。さら
に、封止樹脂が硬化した後に、ヒートショック等の信頼
性試験を行うと、スルホール内の樹脂と導体の熱膨張率
の違いによって導体が切断される可能性もある。その他
、ＩＣ基板を他の銅張り積層板などにハンダ融着によっ
て接合する場合にも、２５０℃程度の熱が加えられるの
で、ヒートショック等の信頼性試験の場合と同じ様にス
ルホール内の導体が切断される可能性がある。Furthermore, if the sealing resin is cured while the sealing resin remains filled in the through-hole, the conductor inside the through-hole may be cut when the sealing resin hardens and shrinks. Furthermore, if a reliability test such as heat shock is performed after the sealing resin has hardened, the conductor may be cut due to the difference in thermal expansion coefficient between the resin in the through hole and the conductor. In addition, when bonding an IC board to another copper-clad laminate by soldering, heat of about 250°C is applied, so conductors inside through-holes are may be disconnected.

これらの原因となる封止樹脂のスルホール内への侵入を
防ぐために、従来は、封止樹脂の種類によってスルホー
ルの径を変えていた。そのため、ＩＣ基板の作成コスト
が高くなっていた。In order to prevent the sealing resin from penetrating into the through-hole, which causes these problems, the diameter of the through-hole has conventionally been changed depending on the type of sealing resin. Therefore, the manufacturing cost of the IC board has increased.

〔発明の目的〕[Purpose of the invention]

以上の点に鑑みて、゛この発明は、表面にＩＣチップが
装着され、裏面に電極が設けられていて、スルホールを
通して、ＩＣチップと電極が電気的に繋がれているＩＣ
基板を封止する際に、封止樹脂の粘度や流れ易さが変わ
っても、スルホールの径を変える必要がなく、封止樹脂
がスルホール内に浸入することのないＩＣ基板の封止法
を提供することを目的とする。In view of the above points, ``this invention is an IC in which an IC chip is mounted on the front surface, an electrode is provided on the back surface, and the IC chip and the electrode are electrically connected through a through hole.
When sealing a board, even if the viscosity or flowability of the sealing resin changes, there is no need to change the diameter of the through hole, and the sealing resin does not infiltrate into the through hole. The purpose is to provide.

〔発明の開示〕[Disclosure of the invention]

前記の目的を達成するため、この発明は、表面にＩＣチ
ップが装着され、裏面に電極が設けられていて、スルホ
ールを通して、ＩＣチップと電極が電気的に繋がれてい
るＩＣ基板を封止する際に、スルホールの少なくとも表
面入口部を塞いでおくことを特徴とするＩＣ基板の封止
法をその要旨とする。以下にこれを、その一実施例をあ
られす図面に基づいて詳しく説明する。In order to achieve the above object, the present invention seals an IC substrate on which an IC chip is mounted on the front surface, an electrode is provided on the back surface, and the IC chip and the electrode are electrically connected through a through hole. The gist of the present invention is a method for sealing an IC substrate, which is characterized by blocking at least the surface entrance portion of the through hole. An embodiment of this will be explained in detail below based on the accompanying drawings.

第３図にみるように、ＩＣ基板１を固定することができ
る治具９を準備する。この治具９には、ＩＣ基板１のス
ルホール５の位置と一致するようニヒン１０が取り付け
られている。ピン１ｏの径は、スルホール５と同径もし
くはそれよりやや小径とし、これをスルホール５に差し
込むことにより、封止樹脂を封止した際に、スルホール
内に封止樹脂が流れ込まないようにする。ピン１ｏの長
さも、スルホール５と同じ長さとし、ピン１０をスルホ
ール５に差し込んだ際にその先端がスルホール５から飛
び出さないようにする。ピン１０の材料は、封止樹脂と
の接着力が弱いもの、例えば、フッ素系樹脂等が好まし
いが、特に限定はしない、治具９とピン１０とは別体で
あってもよいが、一体に形成されていてもよい、ピン１
０の形状は、スルホール５に差し込んだ際に、スルホー
ル５の表面入口部を塞ぐようでありさえすればよい、第
３図中のＩＣチップが装着されたＩＣ基板は、第１図と
同じものを示す、そのため、第１図と同じ番号を付して
いる。As shown in FIG. 3, a jig 9 capable of fixing the IC board 1 is prepared. A pin 10 is attached to this jig 9 so as to match the position of the through hole 5 of the IC board 1. The diameter of the pin 1o is the same as or slightly smaller than that of the through hole 5, and by inserting it into the through hole 5, when the sealing resin is sealed, the sealing resin does not flow into the through hole. The length of the pin 1o is also the same as that of the through hole 5, so that when the pin 10 is inserted into the through hole 5, its tip does not come out from the through hole 5. The material of the pin 10 is preferably a material with weak adhesion to the sealing resin, such as a fluorine-based resin, but is not particularly limited. The jig 9 and the pin 10 may be separate, but may be integrated. pin 1, which may be formed in
The shape of 0 only needs to be such that it closes the surface entrance of the through hole 5 when inserted into the through hole 5. The IC board on which the IC chip in FIG. 3 is mounted is the same as that in FIG. 1. Therefore, the same numbers as in FIG. 1 are given.

このような治具９を用い、第４図にみるように、ＩＣ基
板１のスルホール５に治具９のピン１０を差し込み、治
具９にＩＣ基板１を固定し、ＩＣチップ２が装着された
ＩＣ基板表面に封止樹脂１１で封止をする。封止樹脂１
１が硬化したのち、治具９を取りはずせば、ＩＣチップ
が装着されたＩＣ基板表面の封止が完了する。Using such a jig 9, as shown in FIG. 4, the pins 10 of the jig 9 are inserted into the through holes 5 of the IC board 1, the IC board 1 is fixed to the jig 9, and the IC chip 2 is mounted. The surface of the IC substrate is sealed with a sealing resin 11. Sealing resin 1
1 is cured, the jig 9 is removed, and the sealing of the surface of the IC substrate on which the IC chip is mounted is completed.

このように、ＩＣチップが装着されたＩＣ基板表面を封
止する際に、封止樹脂が硬化するまで、ＩＣ基板のスル
ホールをピンで塞いでいるため、スルホール内に封止樹
脂が流れ込むようなことが起こらないのである。In this way, when sealing the surface of an IC board on which an IC chip is mounted, the through holes of the IC board are covered with pins until the sealing resin hardens, so there is no possibility that the sealing resin will flow into the through holes. It doesn't happen.

このような治具を多数連続させることで、ＩＣＣ史上作
業自動化に寄与することも可能である。By connecting a large number of such jigs in succession, it is possible to contribute to the automation of work in the history of ICC.

スルホールは、少なくとも、その表面入口部が塞がれれ
ばよい、スルホールを塞ぐ手段はピン以外の手段によっ
てもよい。It is sufficient that at least the surface entrance portion of the through hole is closed, and the means for closing the through hole may be other than a pin.

〔発明の効果〕〔Effect of the invention〕

この発明にかかるＩＣ基板の封止法は、ＩＣ基板を封止
する際に、スルホールの少なくとも表面入口部を塞ぐよ
うにしているため、封止樹脂の粘度や流れ易さが変わっ
ても、スルホール内に封止樹脂が侵入することがな（、
封止樹脂の種類によってスルホールの径を変える必要も
ない、スルホール内に封止樹脂が侵入することがないた
め、スルホールへの樹脂侵入に起因するＩＣＣ基板裏型
電極導通不良や、スルホール内の導体の切断を防止する
ことができ、ＩＣチップが装着されたＩＣ基板の信頼性
を向上させることができる。In the method for sealing an IC substrate according to the present invention, when sealing an IC substrate, at least the surface entrance portion of the through hole is blocked, so even if the viscosity or flowability of the sealing resin changes, the through hole The sealing resin will not enter the inside (,
There is no need to change the diameter of the through-hole depending on the type of sealing resin, and since the sealing resin does not invade into the through-hole, it is possible to prevent poor conduction of the back electrode of the ICC board due to resin intrusion into the through-hole, and conductor inside the through-hole. The reliability of the IC board on which the IC chip is mounted can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）はＩＣ基板の一例をあられす斜視図、第１
図（ｂ几よ同上の反対面より見た斜視図、第２図は第１
図（ａ）のＩＣ基板のスル水−ル部を拡大した斜視図、
第３図はこの発明にかかるＩＣ基板の封止法の一実施例
に用いられる治具とＩＣ基板をあられす斜視図、第４図
はこの発明の封止法における樹脂封止後の状態をあられ
す斜視図である。 １・・・ＩＣ基板　２・・・ＥＣチップ　５・・・スル
ホール　８・・・電極　９・・・治具　１０・・・ピン
代理人　弁理士　　松　本　武　彦 （ａ） 第３図 第２図 第４図Figure 1(a) is a perspective view of an example of an IC board.
Figure (a perspective view from the opposite side of the same as above, Figure 2 is
An enlarged perspective view of the through water hole part of the IC board in Figure (a),
Fig. 3 is a perspective view of a jig and an IC board used in an embodiment of the IC board sealing method according to the present invention, and Fig. 4 shows the state after resin sealing in the sealing method of the present invention. It is a hail perspective view. 1... IC board 2... EC chip 5... Through hole 8... Electrode 9... Jig 10... Pin agent Patent attorney Takehiko Matsumoto (a) Figure 3 Figure 2 Figure 4

Claims (3)

【特許請求の範囲】[Claims] （１）表面にＩＣチップが装着され、裏面に電極が設け
られていて、スルホールを通して、ＩＣチップと電極が
電気的に繋がれているＩＣ基板を封止する際に、スルホ
ールの少なくとも表面入口部を塞いでおくことを特徴と
するＩＣ基板の封止法。(1) When sealing an IC substrate in which an IC chip is mounted on the front surface and an electrode is provided on the back surface, and the IC chip and the electrode are electrically connected through the through hole, at least the surface entrance part of the through hole is sealed. A method for sealing an IC board, which is characterized by blocking the . （２）スルホールを塞ぐものが、スルホールと同径のピ
ンである特許請求の範囲第１項記載のＩＣ基板の封止法
。(2) The method for sealing an IC substrate according to claim 1, wherein the thing that closes the through hole is a pin having the same diameter as the through hole. （３）スルホールを塞ぐピンが、スルホールと同じ長さ
になるように形成されていて、ＩＣ基板を固定すること
ができる治具にスルホールの位置と一致するようにして
取り付けられている特許請求の範囲第１項または第２項
記載のＩＣ基板の封止法。(3) The pin that closes the through hole is formed to have the same length as the through hole, and is attached to a jig that can fix the IC board so as to match the position of the through hole. A method for sealing an IC substrate according to item 1 or 2.
JP24200684A 1984-11-15 1984-11-15 Method of sealing ic substrate Pending JPS61120430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24200684A JPS61120430A (en) 1984-11-15 1984-11-15 Method of sealing ic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24200684A JPS61120430A (en) 1984-11-15 1984-11-15 Method of sealing ic substrate

Publications (1)

Publication Number Publication Date
JPS61120430A true JPS61120430A (en) 1986-06-07

Family

ID=17082854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24200684A Pending JPS61120430A (en) 1984-11-15 1984-11-15 Method of sealing ic substrate

Country Status (1)

Country Link
JP (1) JPS61120430A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486566A1 (en) * 1989-08-10 1992-05-27 Olin Corporation Process plate for plastic pin grid array and method of making

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486566A1 (en) * 1989-08-10 1992-05-27 Olin Corporation Process plate for plastic pin grid array and method of making

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