JPS61120258A - Data transfer device - Google Patents

Abstract

PURPOSE:To decrease the generation of data overrun phenomena by continuing the transfer of data with the next channel command word and with no use of a microprogram after the transfer of data is over by the channel command word held by a memory. CONSTITUTION:The 1st memory 2 holds 1 channels command words given from a microprogram. When the data are chained by the command words held by the memory 2, the data are supplied to the 2nd memory 5 which holds the channel command words to beexecuted after the command words held by the memory 2 through a data line 18. The output of the memory 5is delivered to a selection circuit 7 via a data line 19. The circuit 7 outputs the data on either one of data lines 10, 14 and 19 by the output of the signal lines 11 and 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a data transfer device used in an information processing device. In particular, the present invention relates to a data transfer device that uses channel command words to transfer data between an input/output device and a main storage device independently of microprogram control.

[Conventional technology]

Conventionally, this type of data transfer device has only one storage means for holding channel command words, and when the channel command words held in this storage form a data chain, the byte count of this channel command word becomes zero. At this point, an interrupt is generated to the microprogram.
Data transfer continued after being given the next channel command word to be executed by the microprogram.

[Problem that the invention seeks to solve]

Therefore, while the microprogram is performing some other processing, the interrupt processing is forced to wait, and data overruns tend to occur because restart of data transfer by the data chain is delayed.

The present invention solves the above-mentioned drawbacks and aims to reduce the occurrence of data overruns during data chaining.

[Means for solving problems]

The present invention provides a first storage means for holding a channel command word given by a microprogram control means, and a control of the microprogram control means independently of the first storage means for holding a channel command word given by a microprogram control means. , a data transfer device comprising means for transferring data between an input/output device and a main storage device, in addition to the first storage device, a channel to be executed next given by the microprogram control means; a channel command word held in the first storage means, comprising a second storage means for holding a command word; and a channel held in the first storage means; means for detecting that the byte count of the command word has become zero, and when it is determined by the above-mentioned means for determining that data chaining is to be performed, and when the above-mentioned detecting means has detected that the byte count has become zero, and means for transferring the channel command word held in the second storage means to the first storage means.

[Effect]

After the transfer using the channel command word held in the first storage device of the data transfer unit is completed, the channel command word in the second storage device of the data transfer unit is transferred to the first storage device, and the next channel command is transferred. To reduce the occurrence of data overruns by continuing word transfer without using a microprogram.

〔Example〕

Next, the data transfer device of the present invention will be explained in detail with reference to the accompanying drawings.

The figure is a block diagram showing a data transfer section according to an embodiment of the present invention. A first storage device 2 that holds channel command words given from a microprogram is connected to a data line 1.
3 to the byte count and data address update circuit 3 of the channel command word and a circuit 6 for detecting that the byte count is zero, and from the byte count and data address update circuit 3 to the data line 14, select It is connected to the first storage device 2 via a circuit 7 and a data line 12. Further, the data chain determination circuit 4 is connected to the first storage device 2 by a signal line 15, and is connected to the AND circuit 8 by a signal line 17. The AND circuit 8 performs a logical product of the output of the circuit 6 connected via the signal line 16 for detecting that the byte count becomes zero and the output of the data chain determination circuit 4 connected via the signal line 17. is connected to control the selection circuit 7 via the signal line 20.

When the channel command word held in the first storage device 2 forms a data chain, the data line 18 is input to the second storage device 5 which holds the channel command word to be executed following this channel command word. It is connected to the selection circuit 7 via the output data line 19. The selection circuit 7 outputs data on either the data line 10.14 or 19 to the data line 12 by controlling the signal line 11 and the signal line 20.

Next, the operation of the present invention will be explained in detail using an example. When the microprogram fetches the channel command word, it commits the channel command word to the data line 10 and instructs the first storage device 2 to set the channel command word on the signal line 10 via the signal line 11. The selection circuit 7 outputs the contents of data &%10 to the data line 12 under the control of the signal line 11, and this data is set in the first storage device 2.

As the data transfer is executed, the channel command word set in the first storage device 2 is subtracted from the hide count by the byte count and data address update circuit 3, and the data address is added or subtracted, and the data line 14 It is added to the selection circuit 7. The selection circuit 7 normally selects the data on the data line 14, and the updated channel command word is set in the first storage device 2. Data transfer is thus performed using the byte count and data address held in the first storage device.

Next, after setting the channel command word in the first storage device 2, the microprogram determines whether or not the channel command word performs a data chain, and if the channel command word is a channel command word that performs a data chain. , fetches the channel command word to be executed next and sets it in the second storage device 5 via the data line 18. If the channel command word held in the first storage device 2 is one for performing a data chain, the output signal line 17 of the data chain determination circuit 4 becomes logic "1".

When the data transfer based on this channel command word progresses and the detection circuit 6 detects that the byte count held in the first storage device becomes zero, the output signal line 16 of the detection circuit 6 becomes logic "1". Become. Therefore, the output of the AND circuit 8 becomes the logic rlJ, and the selection circuit 7
becomes logic "1", the contents of the data line 19 are output to the data line 12, and as a result, the second storage device 5
The channel command word held in is transferred to the first storage device. As a result, after data transfer based on the channel command word held in the first storage device 2 is completed, the data transfer unit 1 transfers data using the channel command word given to the second storage device 5. Continue.

In the data transfer device of the above embodiment, there is one storage device that holds the channel command word to be executed after the data chain, but this can be expanded to a plurality of storage devices to implement the present invention in the same way.

〔Effect of the invention〕

As explained above, the data transfer unit of the data transfer device of the present invention transfers the channel command word of the second storage device to the first storage device after the transfer using the channel command word held in the first storage device is completed. By configuring the configuration so that the data is transferred to the storage device of the next channel command word and the transfer using the next channel command word can be continued without going through the microprogram, the data can be transferred continuously, thereby reducing the occurrence of failures such as data overruns. It has the effect of

[Brief explanation of drawings]

The figure is a block configuration diagram showing a data transfer section of a data transfer device according to an embodiment of the present invention. ■...Data transfer unit, 2...First storage device, 3.
・Byte count and data address update circuit,
4... Data chain determination circuit, 5... Second storage device, 6... Circuit that detects that the byte count is zero. 7... Selection circuit, 8... AND circuit, 10
．． 12.13.14.18.19...Data line, 1,
15.16.17.20...Signal line.

Claims (1)

[Claims] (1) A first storage means for holding a channel command word given by the microprogram control means, and an input device which is controlled independently of the microprogram control means according to the channel command words sequentially read from the storage means. In a data transfer device comprising means for transferring data between an output device and a main memory device, in addition to the first storage means, a channel command word to be executed next given by the microprogram control means is provided. means for determining whether or not the channel command word held in the first storage means is data chained; and a channel command word held in the first storage means. means for detecting that the byte count has become zero; and when the above determining means determines that data chaining is to be performed, and the detecting means detects that the byte count has become zero, the above-mentioned and means for transferring channel command words held in the second storage means to the first storage means.