JPS61120249A - Deadman's timer circuit - Google Patents

Abstract

PURPOSE:To decide the runaway of a CPU and to reset this CPU for restoration by detecting that the waveform of a cyclic pulse sent from the CPU is deviated from a prescribed form. CONSTITUTION:A CPU1 detects the runaway of a deadman's timer circuit and restores it, and a pulse signal showing the normalcy is transmitted through an output terminal OUT of the CPU1. The normalcy is decided from the pulse width. In a normal mode the level 'H' lasts for a period T1 and then the 'L' level lasts for a period T2. These two levels are repeated cyclically. The generation of a runaway is decided, when the fundamental rule of the waveform of said pulse signal is lost. Then a reset signal is inputted to a reset terminal of the CPU1. No resetting action is carried out with the level 'H' held in a normal mode. Then an active state is started to reset the CPU1 when a pulse of 'L' is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timer circuit for detecting and restoring computer runaway.

((!Future technology) Computer information! 1 While the system is operating normally, the content of the output suddenly loses continuity and change, and after that it outputs incorrect and meaningless information)! ! It may continue to output without any hesitation,
This is generally referred to figuratively as the day of computers. In d-running, the contents (bit concurrence) of various registers in CPt and ' are changed due to external factors such as temporary noise, which may cause the program execution order to be out of order or the memory address to be read to change. This is due to the fact that normal execution of the program is prevented by the CPU register I!, and is not a computer malfunction. After resetting all Y and returning to a blank slate, the program is restarted from the beginning again for one day.

The maximum number of microcomputers is each fl l/+ 101
As it is incorporated into systems and used, it is often used under 51 environmental conditions with many types of noise and VJ, etc., and runaway prevention measures for the operation of these systems are mI! This is a serious problem, and various means for detecting and recovering from runaway have been devised and put into practical use from both hardware and software perspectives.

Hardware runaway detection and recovery means are generally performed by installing a timer within the CPU.

A timer is an automatic clock device that supplies a clock signal to measure the apparent elapsed time of events that occur during CPU operation, for example, in milliseconds. By setting this, it can be used to detect runaway behavior.

FIG. 3 is a circuit diagram of a typical deadman timer as a conventional timer for detecting and restoring funds. In this case, the CPU 10 rarely outputs a pulse signal representing the progress of the process 9 from the output terminal OUT. If the period of this pulse signal is a predetermined period, the deadman timer
In , no processing is performed assuming that the above event is being executed normally, but when the pulse I! When the first period becomes short, it is determined that there are 6 runs, and a signal is applied to the CPUIO terminal RESET to reset the CPU.

To briefly explain the operation of the circuit in Figure 3, first, what is the pulse signal from terminal 0tJT? ! ! RV cc, resistor R1, capacitor C1, and resistor R2 are applied to the CR charging/discharging circuit, and when the voltage at terminal OUT is at a high level (hereinafter referred to as "H"), capacitor C1 is charged by power supply VCC and becomes low. level (hereinafter referred to as "L"), the voltage of the capacitor C1 increases according to the time constant determined by the capacitor 1flC1 and the resistor !R2.During the above charging N0 operation, the voltage at the connection point P1 between the resistor R2 and the capacitor C1 Changes based on the charge and discharge cycle, resistor R3, diode D
1 to the base of transistor R1.

If the period of "H" and "L" of the output terminal OUT (i.e., rEIFtl of the output cover tres) is a predetermined value, it is sufficient to charge the capacitor C1 in 7!i time, while discharging is performed slowly. The voltage across the capacitor C1 remains constant, so the voltage at the point P1 is low, and the transistor R1 remains off.As a result, the voltage across the transistor Tr1 (point P2) is °H''', and the voltage at the point P1 remains off. !Breadboard A
Since the inverting input (-) of the inverting input (-) becomes a higher voltage than the non-inverting input (-), its output becomes -, and the transistor Tr3 remains off, and the terminal RES of the CCP U 10 remains off.
Since the ETI remains at "H-", the recycler 11~ will not be applied to the CPU IO.

Next, when the cycle of the pulse signal at the output terminal OUT of the CPU 10 becomes smaller than a predetermined value, the charging of the capacitor C1 stops.
Since the time becomes shorter, the voltage of the capacitor 01 becomes lower, and as a result, the voltage of the point P1 increases by 1. This turns on the transistor T18. When the transistor Tr1 turns on, F:! , P2 becomes "L" and the output to the bullet amplifier becomes °゛H. As a result, 1-range disk Tr3
is turned on and the CPU 10 is reset.

The deadman timer described above is effective when the period of the output pulse becomes shorter than the normal value, but it has the disadvantage that it does not work when it becomes longer or when the pulse remains H' or "L" without outputting a pulse. .

(@Problems to be Solved) It is an object of the present invention to provide a deadman timer circuit which eliminates the drawbacks of the above-mentioned prior art and can detect and recover from any runaway.

[Means for Solving the Problems] The deadman timer circuit according to the present invention receives 1319! from the CPU during normal operation. Receives a periodic pulse signal that has a δ level during the interval T1 and a low level during the period T2 following the 11 interval T1, and when the waveform of this pulse No. 7 deviates from the above, it is determined to be a runaway and the CPU is reset. A first signal generation circuit which is an old runaway detection circuit and outputs a signal that rises in response to the rise of the pulse signal and falls after maintaining the peak level of period 17\IT1, and the pulse signal Falling in accordance with the falling of the light I! a second signal generation circuit that outputs a signal that rises after maintaining a low level for 5T2, and exclusive OR of each output signal of the first and w42 signal generation circuits and the pulse signal from the CPU; and a circuit that generates a signal for resetting the CPU based on a pulse generated at the output of one of the circuits for calculating exclusive OR.

[Effect]

In the above-mentioned deadman timer circuit, when CPLJ is normal, the output waveforms of the first and second signal generation circuits are the same as the waveforms supplied from CPLJ, so the output from each exclusive OR circuit is always It remains low and therefore no signal is generated to reset the CPU.

However, if the period of the signal supplied from CPtJ becomes shorter (or longer) than normal, or the signal level remains high or low, the pulses in the output signals of the first and second signal generation circuits There is a difference between the rising or falling timing of CPtJ and the rising or falling timing of the pulse signal supplied from CPtJ, and a high-level pulse with a width corresponding to that difference is output from one of the exclusive OR circuits. signal, which resets the CPLI.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows part 1 of the deadman timer circuit according to the present invention! It is a circuit diagram of an example.

Reference numeral 1 indicates CPLJ, which is the object of the runaway detection and recovery operation of this deadman timer circuit, and outputs a pulse signal representing the normality of the occurrence of a predetermined event from the output terminal 0LJT. The measure of this normality is the pulse width, and when normal, ``H-
Level 1 of jf1 question TI! ! It is set so that the continuous "L" level continues for w1 and T2 and is repeated periodically. Runaway is determined when the IPJ of the waveform of this pulse signal collapses. The RESETI child of CPU1 indicates the input terminal of the reset signal, and the par above the RESET character indicates that this terminal is held at "H" during normal operation and no reset operation is performed, but when the pulse of L''' is When inputting e
This indicates that the state is J'ff and CP Ll 1 is reset.

Reference numerals 2 and 3 are stable multivibrators (mono stable multivibrators, written as "mono multi"), and each input terminal A is connected to the terminals Of and IT of CPIJl. The input terminals B of the monomultis 2t9 and 3 are connected to be held at H' and L''', respectively.

In the monomulti 4-2, when the terminal 6 goes to the "H" level, the output terminal Q goes to the "H" level, and the capacitor C1 and the resistor are connected so as to maintain the "H" level during the period T1 and then return to the "L" level. ! A time constant is selected by R1.

The monomulti 3 is connected to the capacitor C2 and the resistor R so that when the level reaches the "L" level, the output terminal σ goes "off" and maintains the "L" level between W1 and T2, and returns to "H".
A time constant of 2 is selected.

The output terminal Q and input terminal A of the monomulti 2 are connected to the two inputs of the exclusive logic circuit 114, and the output terminal Q and the input terminal A of the monomulti 3 are connected to the two input terminals of the exclusive OR circuit 5.
connected to two inputs. Each output of exclusive OR circuits 15 and 5 is connected to each input of OR circuit 6, and the output of OR circuit 6 is connected to input terminal A of monomulti 7. The functionality of MonoMulti 7 is similar to MonoMulti 2, and capacitor C3I3 and resistor R3 are selected to provide an appropriate pulse width to reset the CPUI.

Monomultis 2.35 and 7 are reset unconditionally when the R8 signal of "L" is input to the terminal CB.

The output terminal Q of the monomulti 7 is connected to one input of the NOR circuit 9. The other input of this NOR circuit 9 is connected to the output of a reset circuit 1o that outputs a reset signal R8. The output of the NOR circuit 9 is the terminal RES of CPtJl.
Connected to ET.

The operation of the circuit causing the first factor will be explained below. FIG. 2 is a timing chart showing an example of temporal changes in the signals placed at the positions marked with circles in the circuit of FIG. Signal S 11. t is the output signal of CPU 1.

As is clear from the lambda performance of each circuit element, the signal 52 (J is a signal that maintains "H" during the rising edge of T1 and falls in response to the rising edge of the signal S1, and the signal S3 falls in response to the falling edge of the signal S1). Accordingly, this is a signal that falls after holding the falling period 'L' of T2.The signal S4 is a period 11 L II in which each level of the signal S1 and signal S2 is the same, and the signal S5 is the signal S1 and the signal @ Period “L” during which each level of S3 is consistent
”. Also, the signal @S6 is “H” during the period when the signal 84 or S5 is “H”. The signal S7 maintains "H" during the rising period T3 in response to the rising of the signal @S6, and then falls.

Assuming that cpu i is normal in the time interval a shown in the second factor, the signal $1 is an I!!1 period signal that becomes H"1 in period 1 and "L"' in period T2, so the signal 52r3 and S3 will be the same as signal S1, so that signals 84, 85, 86, 37 will both remain at 'L' and therefore CPU 1 will not be reset.

Section 115b shows a case where the first half period of signal S1 is shorter than T1, and at this time, there is a difference in the falling timing of signals S1 and $2, and this “H” pulse with a width of 4 is applied to signal S4. appear. No pulses occur in signal S5. The pulse of the signal S4 becomes the pulse of the signal S6, and the rise of this pulse forms the reset pulse of the signal S7, thereby resetting the CPU 1.

Period C indicates a case where the second half of the cycle of signal @S1 is shorter than T2. In this case, there is a difference in the rise of signals S1 and 83, and a pulse with the width of this difference appears in signal S5, which becomes signal $6. , due to the rise of this signal S6, the signal S7
rises, and as a result, CPL 11 is reset.

Ward 1'0! d shows the case where the signal $1 goes to "H" and continues, and the signal $2 rises (rises) and holds "H" for the period T1, then falls and remains "off". Shin83 is 11
The signal that rises after 11i8T2 remains at "H". As a result, in this period dl, :r), the signal @S4 becomes H°° except for the first period T1, and one signal S5 becomes “L”.
The signal @S4, which remains as ``, becomes the signal S6 as it is, and in response to the rise of this signal S6, the reset @S7 rises and resets the CPU1.

1115g shows the case where the signal S1 remains at "L", and the signal $3 remains at "L" during the first falling period III!T2 and then remains at "H" after falling. Therefore, the signal S2 remains at "L". Therefore, the signal S4 remains falling, and the signal S5 remains at "H" except for the first period T2 of l&.As a result, the period T2 during the first w4 of R At the end, the signal S6 rises, and in response, the reset pulse S7 rises and resets the CPU1.

〔effect〕

The deadman timer circuit according to the present invention emits the pulse signal not only when the period of the pulse signal from the CPU becomes short, but also when it becomes long or when it remains at the "H" level or "L" level. Since the CPU can be reset at any time, a wide range of runaway disturbances can be handled, and it also provides cost-effective runaway detection and an old method.

[Brief explanation of the drawing]

The first factor is a circuit diagram of a practical embodiment of the present invention, and FIG. 2 is a signal timing chart for explaining the VJ operation of the circuit in FIG.
jF! FIG. 3 is an F8 diagram of a conventional deadman timer. 1...CPU, 2...'M1 signal generation circuit, 3...
Kiku 2 signal generation circuit, 4.5...Circuit for calculating exclusive OR, 6.7
．． 9...Circuit that generates a signal to reset the CPU. Applicant: NEC Home Electronics Co., Ltd.

Claims (1)

[Claims] 1. A periodic pulse signal is received from the CPU which is at a high level during a period T1 during normal operation and is at a low level during a period T2 following this period T1, and the waveform of this pulse signal deviates from the above. a runaway detection and recovery circuit that sometimes determines a runaway and resets the CPU; a signal generation circuit; a second signal generation circuit that outputs a signal that falls in response to the fall of the pulse signal, maintains a low level for a period T2, and then rises; and the first and second signal generation circuits. A circuit that calculates each exclusive OR of each output signal of the circuit and a pulse signal from the CPU, and a reset of the CPU based on a pulse generated in the output of any one of the circuits that calculates each of these exclusive ORs. A deadman timer circuit comprising: a circuit for generating a signal for the deadman timer circuit;