JPS61116838A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS61116838A
JPS61116838A JP59239102A JP23910284A JPS61116838A JP S61116838 A JPS61116838 A JP S61116838A JP 59239102 A JP59239102 A JP 59239102A JP 23910284 A JP23910284 A JP 23910284A JP S61116838 A JPS61116838 A JP S61116838A
Authority
JP
Japan
Prior art keywords
resist
resist film
substrate
light
ultraviolet light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59239102A
Other languages
Japanese (ja)
Inventor
Naoyuki Sugiura
杉浦 直幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP59239102A priority Critical patent/JPS61116838A/en
Publication of JPS61116838A publication Critical patent/JPS61116838A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve rectangularity of section by transferring a mask pattern using near ultraviolet ray beam to a resist film on an Si substrate, giving far ultraviolet ray beam to the entire part and executing the development processing. CONSTITUTION:A positive UV resist film 2 of mixture of novolac resin and orthoquinondiazide is formed on a Si substrate 1. It is baked for 100sec from the rear side of substrate at 70-80 deg.C. Thereafter, the surface is irradiated with near UV ray 4 in the wavelength of 320nm or more through the mask 3 and thereby the resist at the exposing part 2b changes to orthoquinondiazide carboxyl acid. Next, the entire part is irradiated with the far UV beam 5 with wavelength of 320nm of less from the rear surface of substrate 1 while heating at 90-110 deg.C, and the resist of unexposed portion 2a absorbs the far UV beam and shows bridging reaction, lowering solubility to the developer. When developed, only the part 2a remains. According to this structure, rectangularity of resist pattern can be improved very easily.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はLSI等の製造技術であるレジストパターン形
成方法に関するもので、レジストパターンの縦断面形状
の角形性を同上させようとするものである。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for forming a resist pattern, which is a manufacturing technology for LSIs, etc., and is intended to improve the squareness of the vertical cross-sectional shape of the resist pattern. be.

(ロノ 従来の技術 LSI製造におけるリング2フイ一工程では、クエハー
(半導体基板)上に、必要なレジスト膜の幾何学的形状
を形成するために、通常、ガラス基板の表面にクロムパ
ターンを配置したマスクと呼ばれるものを用いて、紫外
線光(UV光)でレジスト膜を塗布した半導体基板上に
転写する方法を株っている。
(Rono) Conventional technology In the ring 2 fin process in LSI manufacturing, a chrome pattern is usually placed on the surface of a glass substrate in order to form the required geometric shape of a resist film on a wafer (semiconductor substrate). We have a method of transferring a resist film onto a semiconductor substrate coated with ultraviolet light (UV light) using something called a mask.

現在、市販されている一般的なポジ9UVレジスト(以
下レジストという)は、アルカリ溶液(現像液)に溶解
するノボラツ、り樹脂(ポリマー)と、オルソキノンジ
アジドと呼ばれる感光剤の混合物である。UV光がレジ
スト膜に照射されると、感光剤であるオルソキノンジア
ジドは、印刷学会出版部発行、角田隆弘著「MS光性樹
脂」%28頁に示されているように第6図に示す反応を
起こし、最終的に、アルカリ溶液に対して極めて溶解度
の高いカルボキシルeを生じる。また、オルソキノンジ
アジドは、ノボラック樹脂のアルカリg液に対する溶解
の抑止剤として働くので、レジスト膜は感光していない
状悪では、アルカリ溶液に対して、極めて溶解度が低い
A typical positive 9 UV resist (hereinafter referred to as resist) currently on the market is a mixture of a novolatile resin (polymer) that dissolves in an alkaline solution (developer) and a photosensitizer called orthoquinonediazide. When the resist film is irradiated with UV light, the photosensitive agent orthoquinone diazide reacts as shown in Figure 6, as shown in "MS Photoresin" by Takahiro Tsunoda, published by Printing Society Publishing Department, page 28. finally produces carboxyl e, which has extremely high solubility in alkaline solutions. In addition, orthoquinone diazide acts as an inhibitor of dissolution of the novolak resin in the alkaline g solution, so if the resist film is not exposed to light, it has extremely low solubility in the alkaline solution.

この=光の照射された領域(露光部)と、元のへ 、j      照射されていない饋H,(未露光部)
の現像液に対する溶解速度の差を利用して、基板上にレ
ジスト膜の幾何学的形成するのが、現在のリングラフイ
ー技術であるが、マスク上に配置されたクロムパターン
を基板上に転写する方法として、光による投影露光方式
を用いているため、光の回折現象により、本来光が照射
されるべきでない領域への光の回りごみが発生し、また
、レジストの溶解速度比(1!光部の溶解速度)/(未
露光部の溶解速度)が、無限大ではなく、有限であるこ
とから、現像後、得られたレジストパターンの断面形状
は、第4図に示したようなものになり、その側壁α)の
、基板(S)に対する傾きは、90°ではない角度θを
持つ。
This = the area irradiated with light (exposed area) and the area that is not irradiated (unexposed area)
Current phosphor-fi technology uses the difference in dissolution rate of chromium in a developer to form a resist film geometrically on a substrate. Since a projection exposure method using light is used as a method of exposure, the diffraction phenomenon of light causes the light to wander into areas where it should not be irradiated, and the dissolution rate ratio of the resist (1! Since the ratio (dissolution rate of the exposed area)/(dissolution rate of the unexposed area) is not infinite but finite, the cross-sectional shape of the resist pattern obtained after development is as shown in Figure 4. , and the inclination of the side wall α) with respect to the substrate (S) has an angle θ which is not 90°.

(ハ)発明が解決しようとする問題点 LSIの製造プロセスは、シリコン基板上に2ける#膜
の形成および、それらのエツチングからなり、プロセス
が進むにつれて、基板表面は、パターンの刻まれた段差
のある形状になる。段屋のある基板面上で、レジストの
塗布、露光、現像を行ない、レジストパターンを形成す
ると、第5図に示したように、半導体基板(S)段差(
(支)をレジスト膜ψ)のラインが横切る場合には、1
lIIJ壁のなす角θのために、段差高をdとすると、
段差の上下で、2d/lanθ の保輻g(Qは片側の
線幅差を示す)を引き起こす。このような線幅の便前は
、製作する素子の許容寸法精度によっては、重大な問題
となる。現在までに、段差による線幅の変動を押さえる
方法として、種々の多層レジスト法が開発されてきたが
、いずれも、良好な寸法精度を与えるかわりに、工程の
増加、すなわち、スループットの低下をもたらし、また
、実用に際して、幾多の高額の新装置が必要であるなど
の欠点があった。
(c) Problems to be Solved by the Invention The LSI manufacturing process consists of forming two # films on a silicon substrate and etching them. It becomes a certain shape. When a resist pattern is formed by coating, exposing, and developing a resist on the surface of the substrate with the steps, the semiconductor substrate (S) has the steps (
When the line of resist film ψ) crosses (support), 1
Because of the angle θ formed by the lIIJ wall, if the height of the step is d, then
A convergence g of 2d/lanθ (Q indicates the line width difference on one side) is caused above and below the step. Setting such a line width poses a serious problem depending on the allowable dimensional accuracy of the device to be manufactured. To date, various multilayer resist methods have been developed as a method for suppressing variations in line width due to step differences, but all of these methods increase the number of steps and reduce throughput, although they provide good dimensional accuracy. In addition, there were drawbacks such as the need for a number of expensive new devices for practical use.

本発明は上記欠点を除去する経済的で、有効なレジスト
パターン形成方決を提供しようとするものである。
The present invention seeks to provide an economical and effective method for forming resist patterns that eliminates the above-mentioned drawbacks.

に)問題点を解決するための手段 零g+は牛尋体基板上のレジスト膜に近紫外線光を用い
てマスクパターンを転写し、その後レジスト膜の近紫外
線光の付与されている部分(露光部)と該近紫外裸光の
付与きれていない部分(未露光部)とに同時に遠紫外裸
光を付与し、次いでレジストsを現像処理するものであ
る。
2) The method for solving the problem is to transfer a mask pattern onto a resist film on a cowhide substrate using near-ultraviolet light, and then transfer the mask pattern to the part of the resist film to which near-ultraviolet light has been applied (exposed part). ) and the area to which the near-ultraviolet naked light has not been applied (unexposed area) at the same time, far-ultraviolet naked light is applied, and then the resist s is developed.

(ホ)作 用 UV光をレジスト(アルカリ溶液に溶解するノボラック
樹8旨(ポリマー)とオルソキノンジアジドと呼ばれる
感光剤の混合物)に照射した場合には、オルソキノンジ
アジドは、イオン解離金して、カルボニクムイオンを発
生するが、遠紫外裸光(DUV光)を照射すると、イオ
ン解i11!ハせずに、極めて反応性の高いラジカルを
発生する。(ラジカルを生みだすために必要な光子1個
当りのエネtLtキーは、3.9eV以上であり、これ
は、光の波長< 320 tea (D U V光)に
対応する。)生成されたラジカルは、ノボラックm所間
に結合を引き起こし、また、ラジカル間でも栢台が完生
じ、分子量が増大する(光栗債反に6)。クロスリンキ
ングして分子量の増大したレジストは、現源漱に対する
溶解性が、未露光の状想よりも者しく低下する。
(e) Effect: When UV light is irradiated onto a resist (a mixture of a novolac resin (polymer) dissolved in an alkaline solution and a photosensitizer called orthoquinonediazide), orthoquinonediazide is converted into ionically dissociated gold and carboxylic acid. Nicum ions are generated, but when irradiated with deep ultraviolet naked light (DUV light), the ions are decomposed i11! Generates highly reactive radicals without causing any damage. (The energy tLt key per photon required to generate radicals is 3.9 eV or more, which corresponds to a wavelength of light < 320 tea (DUV light).) The generated radicals are , causing bonding between the novolac m, and also forming a hologram between radicals, increasing the molecular weight (6). A resist whose molecular weight has increased due to cross-linking has a markedly lower solubility in Gengen Soybean than an unexposed resist.

UVll1¥光をした後、半尋体基板全■にDUViJ
党を行なうと、次のような現象が見込まれる。
After applying UVll1¥ light, apply DUViJ to the entire half-body board.
When you hold a party, you can expect the following phenomena.

がカルボキシ酸に変化してしまっている露光部でほDU
V照射によるクロスリンキングは発生しないので、露光
部、未露光部の選択的なりロスリンキングかり能でるり
、未露光部の溶解速度だけを小さくすることかでさる。
DU in the exposed area where has changed to carboxylic acid.
Since cross-linking does not occur due to V irradiation, loss-linking can be achieved selectively between the exposed and unexposed areas, or by reducing the dissolution rate of only the unexposed areas.

■ DUv光は、レジストに対して大きな吸収係数を持
つ。
■ DUv light has a large absorption coefficient for resist.

−1として、入射光の強度が1/10になるレジスh+
漢f!i−#計算すると、e、長200〜245nm及
び275士10nmでは、100OA、255士10n
mでは5000A、290〜300nmでは、jsoo
o人である。(段差高の大きい基板上でレジストパター
ンを形成する場合に選択するレジスト膜厚は15000
λ程度である。)υUv光のレジストに対する高い吸収
性のために、クロスリンキングの発生する利金は、レジ
スト膜と半導体基板の境界圓から、レジスト膜と犬) 
    気の境界曲へ行くに従って指奴関故的に増加し
、t( レジスト膜の上層部はど、等解速度が小さくなる。
-1, the register h+ where the intensity of the incident light is 1/10
Han f! i-# calculation, e, length 200-245nm and 275-10nm, 100OA, 255-10n
5000A for m, jsoo for 290-300nm
There are o people. (When forming a resist pattern on a substrate with a large step height, the resist film thickness selected is 15,000.
It is about λ. ) Due to the high absorption of υUv light into the resist, the cross-linking occurs from the boundary circle between the resist film and the semiconductor substrate, and from the resist film and the semiconductor substrate.
As we move towards the boundary curve of the air, the velocity increases due to t(t).In the upper layer of the resist film, the isostatic velocity becomes smaller.

■ DLIV光の照射では、新たなカルボキシルdは発
生−亡ず、レジスト膜は感光しない。
(2) Upon irradiation with DLIV light, new carboxyl d is generated and not destroyed, and the resist film is not exposed to light.

以上のことから、DUV照射により、レジストの溶解速
度比(露光部の溶解速度)/(未露光部の溶解速度)は
犬さくなり、また、末認光部の溶解速度は、レジストの
上層部はど小さくなって、現像後のパターンの側壁がな
す角度θは大さくなる。この結果、レジストラインが段
差を横切る場合の線幅変鰐は、通常のプロセスで得られ
るものよりも小さくなると考えられる。
From the above, with DUV irradiation, the dissolution rate ratio of the resist (dissolution rate of the exposed area)/(dissolution rate of the unexposed area) becomes smaller, and the dissolution rate of the exposed area becomes smaller than that of the upper layer of the resist. The angle θ formed by the sidewalls of the pattern after development becomes larger. As a result, line width variation when a resist line crosses a step is considered to be smaller than that obtained by a normal process.

(へ)実施例 第1図は零発明方去の工程図を示すものであるウシリコ
ンクエハなどの半導体基板(1)の111ilにノボラ
ック樹脂と感光剤(オルソキノンジアジド)の混合物で
あるポジ型UVレジスト(例えば、東京応化体製の0F
PR−800CJ’を塗布してレジスト膜(2)t−形
成する(第1工程、第1図A)。次いで、この半導体基
板(1)をダイレクトホットプレート型ベーク装置!を
用いて、瓢に70〜80℃で該基板の背向側から100
秒間ベーキングする(、第2工程、第1図B)。このベ
ーク処理におけるべ−り温度を比較的低く(通常のプロ
セスでは90〜110℃程度)設定しているのは後の工
程で再度ベーク処理を行なうため通常プロセスと同様の
処理tしていては熱による感光剤の分解およびレジスト
膜(2)中の溶剤の揮発が過多となってレンス)[の光
に対する感度が低下し、スループットが低下するからで
ある。
(f) Example Figure 1 shows a process diagram of the zero invention method.A positive UV resist (111il), which is a mixture of a novolac resin and a photosensitizer (orthoquinonediazide), is applied to a semiconductor substrate (1) such as a silicon wafer. For example, 0F manufactured by Tokyo Ohkatai
PR-800CJ' is applied to form a resist film (2) (first step, FIG. 1A). Next, this semiconductor substrate (1) is placed in a direct hot plate baking device! 100° from the back side of the substrate at 70 to 80°C using
Bake for 2 seconds (second step, Figure 1B). The reason why the baking temperature in this baking process is set relatively low (about 90 to 110°C in normal processes) is because the baking process will be performed again in the later process, so it is not necessary to use the same process as in the normal process. This is because the decomposition of the photosensitizer and the volatilization of the solvent in the resist film (2) due to heat become excessive, resulting in a decrease in the sensitivity of the lens to light and a decrease in throughput.

次に、上記半導体基板(1)のレジスト膜(2)にマス
ク(3)を介してUV光を用いた露光装置でUV光(4
)(波長が320nm以上の近紫外光)を照射する。
Next, an exposure device using UV light is applied to the resist film (2) of the semiconductor substrate (1) through a mask (3).
) (near ultraviolet light with a wavelength of 320 nm or more).

マスクX3)はマスク基板(6a)上クロム製のパター
ン(6b)を有しており、このパターン(3b)に対向
するレジスト膜の部分(2a)にUV光を照射せず一方
このパターンが存在しない部分に対向するレジスト膜の
都か(2b)にUV″Lを照射するようにしている。上
述のように!先部分(2b)上のレジスト膜ではオルソ
キノンジアジドがカルボキシル酸に変化してし筐ってい
る。一方、未露光部分(2a)ではこのような変化が生
じていない(第3工程、第1図C)。
Mask X3) has a chrome pattern (6b) on the mask substrate (6a), and the part (2a) of the resist film facing this pattern (3b) is not irradiated with UV light, while this pattern exists. UV''L is irradiated to the resist film (2b) opposite to the non-containing part.As mentioned above, orthoquinonediazide is converted to carboxylic acid in the resist film on the front part (2b). On the other hand, no such change occurs in the unexposed portion (2a) (third step, FIG. 1C).

次いで、半昇体基板Ill上のレジスト膜(2)の露光
部分(2b)及び未露光部分(2a)にlL艮が620
nmより小さい遠紫外裸光(DUv″”Jt、 ) !
51を、該基板(1)?その背向側から加熱しながら照
射する(第4工程、第1図D)。このDUV光の照射に
よって上記未露光部分(2a)は露光されないが、この
DUV光を吸収して架橋反応を呈し、その結実現像液に
対する溶解性が低下さA(るっ尚、この第4工程でのベ
ーキングはクロスリンギングを促進させ、DUV%理時
間全時間させるために行なわれている。ベーク温度はレ
ジストの種類によって軟化温度(この温度を超えるとレ
ジストが流れ始める)に差があるため一義的に定まらな
いが、現在良く使用されているものに対しては90〜1
10℃が適当である。向、第4工程は市販されているD
UV光全面露光装置(FUSI(IN SEMICON
DUCTORSYSTEM C0RPのMICROLI
TE PH0TO5TABILIZERMODEL  
12(SPCなどンを用いて実施され、60秒程度のD
Uv光の照射でレジスト膜12)の未露光部分のクロス
リンギングを得ることができる。現像は上記UVレジス
トに対して効果的な現像液(例えばNMD 2.68%
)全便って行なわれる(第5工程、fJi図E)。半導
体基板11)上のレジスト膜の近UV光が付与されてい
る部分のみが除去され、未露光部分が残される。第2図
は現像後の半導体基板の部分拡大断面図である。図中、
破線で示す従来例に比べてレジスト膜の角形性が向上さ
れる。それ改、このレジスト膜が半導体基板上の設差部
分を交差して配役されてもこの段差の上下でレジスト膜
の@幅が大さく変妨すゐことV′iない。
Next, 620 llL stripes were applied to the exposed portion (2b) and unexposed portion (2a) of the resist film (2) on the semi-substrate substrate Ill.
Far ultraviolet naked light (DUv''''Jt, ) smaller than nm!
51, the substrate (1)? Irradiation is performed while heating from the back side (fourth step, FIG. 1D). Although the unexposed area (2a) is not exposed to light by this irradiation with DUV light, it absorbs this DUV light and exhibits a crosslinking reaction, reducing its solubility in the imaging solution. Baking is performed to promote cross-ringing and extend the DUV% processing time to the full time.The baking temperature is important because the softening temperature (beyond this temperature, the resist begins to flow) differs depending on the type of resist. The standard is not determined, but it is 90 to 1 for those commonly used at present.
10°C is suitable. For the fourth step, commercially available D
UV light full surface exposure equipment (FUSI (IN SEMICOND)
MICROLI of DUCTORSYSTEM C0RP
TE PH0TO5TABILIZERMODEL
12 (conducted using SPC etc., D for about 60 seconds
By irradiating with UV light, it is possible to obtain cross ringing in the unexposed portions of the resist film 12). Development is carried out using a developer effective for the UV resist (for example, NMD 2.68%).
) The whole flight is carried out (5th step, fJi diagram E). Only the portion of the resist film on the semiconductor substrate 11) to which the near-UV light has been applied is removed, leaving the unexposed portion. FIG. 2 is a partially enlarged sectional view of the semiconductor substrate after development. In the figure,
The squareness of the resist film is improved compared to the conventional example shown by the broken line. In addition, even if this resist film is placed across the stepped portion on the semiconductor substrate, the width of the resist film above and below the step will not change significantly.

尚、上記角形性の向上はDUV光によるレジスト膜のク
ロスリンギングが、未ば元部の、さらにレジスト膜の表
面側はど現像液に対する溶解性を低下させるために達成
きれるものである。
The above-mentioned improvement in squareness can be achieved because cross-ringing of the resist film caused by DUV light lowers the solubility of the original portion and the surface side of the resist film in a developing solution.

(ト)発明の効果 以上説明したように本発明は半導体基板上のしう   
   シスト漢にマスクを用いて近索外保光と付与して
j 選択面にU党し、その後この露光部分及び未露光部分に
同時に遠紫外線光を照射して、未露光部分の表層側の、
現像液に対する溶解性を小さくしているので、現像恢の
レジストパターンの縦断面の角形性を極めて簡単に向上
することかできろうすなわち、工程として増えるのは1
回のDUV照射工程だけであり、また、析たに必要な装
置はDUV蕗光装置i+t+台だけである。
(g) Effects of the invention As explained above, the present invention provides
Using a mask to protect the cyst from the outside, apply it to the selected surface, then irradiate the exposed and unexposed areas with deep ultraviolet light at the same time, and remove the surface layer of the unexposed area.
Since the solubility in the developer is reduced, the squareness of the vertical cross section of the resist pattern after development can be improved very easily.In other words, the number of additional steps is 1
Only one DUV irradiation process is required, and the only equipment required for analysis is a DUV irradiation device i+t+.

【図面の簡単な説明】[Brief explanation of drawings]

S+図A−Eは本@明方去の工程図、第2図は現像工程
終了後の半導体基板の部分断面図、第6図はレジスト膜
中の感光剤の、UV光に対する光分解t!4程図、%4
図は従来方法によるレジストパターンの縦断面図、45
図A%Bflこのレジストパターンを何する半導体基板
の平曲図とv−■断面図である。 11)・・・半導体基板、(2)・・・レジスト膜。
S+ Figures A-E are process diagrams of Hon@Meikagayo, Figure 2 is a partial cross-sectional view of the semiconductor substrate after the development process, and Figure 6 is photolysis of the photosensitive agent in the resist film against UV light t! 4 degree diagram, %4
The figure is a vertical cross-sectional view of a resist pattern obtained by a conventional method.
Figure A%Bfl is a flat curved view and a v--2 sectional view of a semiconductor substrate using this resist pattern. 11)...Semiconductor substrate, (2)...Resist film.

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板の1面上にレジスト膜を付設する第1
工程と、該半導体基板上の前記レジスト膜を加熱する第
2工程と、前記レジスト膜上にマスク上のパターンに従
がい近紫外線光を選択的に付与する第3工程と、前記レ
ジスト膜の前記近紫外線光の付与されている部分と該近
紫外線光の付与されていない部分とに同時に遠紫外線光
を付与する第4工程と、前記レジスト膜の前記近紫外線
光の付与されている部分を除去する第5工程とを備える
レジストパターン形成方法。
(1) A first step in which a resist film is attached on one surface of a semiconductor substrate.
a second step of heating the resist film on the semiconductor substrate; a third step of selectively applying near-ultraviolet light to the resist film according to a pattern on a mask; a fourth step of simultaneously applying far-ultraviolet light to a portion to which near-ultraviolet light has been applied and a portion to which the near-ultraviolet light has not been applied, and removing the portion of the resist film to which the near-ultraviolet light has been applied; A resist pattern forming method comprising: a fifth step of forming a resist pattern;
(2)前記第4工程は前記レジスト膜を加熱しながら実
施されることを特徴とする特許請求の範囲第(1)項記
載のレジストパターン形成方法。
(2) The resist pattern forming method according to claim (1), wherein the fourth step is performed while heating the resist film.
(3)前記第2工程における加熱条件は第4工程におけ
る加熱条件に比べて低温に設定されており、70〜80
℃の範囲で設定されていることを特徴とする特許請求の
範囲第(2)項記載のレジストパターン形成方法。
(3) The heating conditions in the second step are set at a lower temperature than the heating conditions in the fourth step, and are set at a temperature of 70 to 80 ℃.
The resist pattern forming method according to claim (2), wherein the temperature is set within a range of .degree.
(4)前記レジスト膜を構成するレジストはアルカリ溶
液に溶解するノボラック樹脂とオルソキノンジアジドの
混合物であり、紫外線光を吸収する染料を添加してなる
ものである特許請求の範囲第(1)又は第(2)又は第
(3)項記載のレジストパターン形成方法。
(4) The resist constituting the resist film is a mixture of a novolac resin and orthoquinone diazide dissolved in an alkaline solution, and a dye that absorbs ultraviolet light is added thereto. (2) or the resist pattern forming method described in item (3).
JP59239102A 1984-11-13 1984-11-13 Formation of resist pattern Pending JPS61116838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59239102A JPS61116838A (en) 1984-11-13 1984-11-13 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59239102A JPS61116838A (en) 1984-11-13 1984-11-13 Formation of resist pattern

Publications (1)

Publication Number Publication Date
JPS61116838A true JPS61116838A (en) 1986-06-04

Family

ID=17039834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59239102A Pending JPS61116838A (en) 1984-11-13 1984-11-13 Formation of resist pattern

Country Status (1)

Country Link
JP (1) JPS61116838A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01243052A (en) * 1988-03-24 1989-09-27 Matsushita Electron Corp Resist pattern forming method
US4933263A (en) * 1987-02-17 1990-06-12 Matsushita Electronics Corporation Forming method of resist pattern
JPH03255613A (en) * 1990-03-05 1991-11-14 Matsushita Electron Corp Resist pattern forming method
JPH054293A (en) * 1990-10-20 1993-01-14 Sumitomo Rubber Ind Ltd Manufacture of green tire and device therefor
US6231024B1 (en) 1998-10-19 2001-05-15 Kabushikikaisha Kugin Formwork forming unit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933263A (en) * 1987-02-17 1990-06-12 Matsushita Electronics Corporation Forming method of resist pattern
JPH01243052A (en) * 1988-03-24 1989-09-27 Matsushita Electron Corp Resist pattern forming method
JPH03255613A (en) * 1990-03-05 1991-11-14 Matsushita Electron Corp Resist pattern forming method
JPH054293A (en) * 1990-10-20 1993-01-14 Sumitomo Rubber Ind Ltd Manufacture of green tire and device therefor
US6231024B1 (en) 1998-10-19 2001-05-15 Kabushikikaisha Kugin Formwork forming unit

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