JPS61115365A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS61115365A
JPS61115365A JP23724984A JP23724984A JPS61115365A JP S61115365 A JPS61115365 A JP S61115365A JP 23724984 A JP23724984 A JP 23724984A JP 23724984 A JP23724984 A JP 23724984A JP S61115365 A JPS61115365 A JP S61115365A
Authority
JP
Japan
Prior art keywords
layer
gaas
type
gaalas
melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23724984A
Other languages
Japanese (ja)
Inventor
Takuro Ishikura
卓郎 石倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP23724984A priority Critical patent/JPS61115365A/en
Publication of JPS61115365A publication Critical patent/JPS61115365A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent deterioration due to heat generation by forming constitution in which a melting-in to a growth layer of an internal current constriction layer is prevented. CONSTITUTION:A GaAs layer 5 is shaped so that a p type GaAlAs clad layer 6 is grown easily in a liquid-phase manner. A GaAlAs layer 4 obviates the melting-in of an n type GaAs layer 3 into the p type GaAlAs clad layer 6 when the layer 6 grows. The melting-in of Ga1-xAlxAs to a Ga solution reduces with the increase of x. Accordingly, when the p type GaAlAs clad layer 6 grows on the GaAs layer 5, a melting-in more than the GaAs layer 5 melts into the layer 6 is prevented by the GaAlAs layer 4 under the layer 5 though the GaAs layer 5 melts into the layer 6.

Description

【発明の詳細な説明】 (イ)発明の目的 〔産業上の利用分野〕 この発明は、半導体レーザなどに見られる、内部に電流
狭窄層を有するQaAs−QaAIAs系の半導体素子
に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Object of the Invention [Field of Industrial Application] The present invention relates to a QaAs-QaAIAs semiconductor element having an internal current confinement layer, which is found in semiconductor lasers and the like.

〔従来技術〕[Prior art]

従来の、内部に電流狭窄層を有する半導体素子は、半導
体基板と、その上に形成され一部をエツチングで除去さ
れる内部電流狭窄層と、この内部電流狭窄層の上に液相
成長法で成長させる各種成長層とから構成される。
A conventional semiconductor element having an internal current confinement layer consists of a semiconductor substrate, an internal current confinement layer formed on the substrate and partially removed by etching, and a liquid-phase growth layer formed on the internal current confinement layer by a liquid phase growth method. It is composed of various growth layers to be grown.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

内部に電流狭窄層をもつ従来の半導体素子では、電流状
5i層の上に各種の成長層を形成する製造工程において
、電流狭窄層が、隣接する成長層に溶は込むことが、し
ばしば見られる。ところで、この電流狭窄層に隣接する
成長層は、一般に、電流狭窄層と反対の導電型を有する
ため、このような溶は込みが生じると、電子濃度が補償
効果によって減少し、成長層が高抵抗化する。この素子
に電流を流すと、この高抵抗化した層が発熱し、素子が
劣化するという問題点があった。
In conventional semiconductor devices that have a current confinement layer inside, it is often seen that the current confinement layer melts into adjacent grown layers during the manufacturing process in which various growth layers are formed on the current-like 5i layer. . By the way, the grown layer adjacent to this current confinement layer generally has a conductivity type opposite to that of the current confinement layer, so when such penetration occurs, the electron concentration decreases due to the compensation effect, and the grown layer becomes high. Become a resistance. When a current is passed through this element, this high-resistance layer generates heat, which causes the element to deteriorate.

また、このような熔は込みは、その接合面において均一
に生じないため、チャンネル形状が均一化されず、素子
の性能のばらつきの原因にもなっていた。
In addition, such weld penetration does not occur uniformly on the bonding surface, so the channel shape is not made uniform, which causes variations in the performance of the device.

この発明は、このような事情に鑑みなされたもので、電
流狭窄層が、成長層に溶は込むことを防止して、発熱に
よる劣化を生じることのないまた性能に均一性のある半
導体素子を提供するものである。
This invention was made in view of the above circumstances, and it is possible to prevent the current confinement layer from penetrating into the growth layer, thereby providing a semiconductor element that does not deteriorate due to heat generation and has uniform performance. This is what we provide.

(ロ)発明の構成 この発明の構成を、第1図を用いて説明する。(b) Structure of the invention The configuration of this invention will be explained using FIG. 1.

半導体素子(101)において、(102)は半導体基
板、(103)は各種成長層、(104)は、半導体基
板(102)と各種成長層(103)との間にあって、
GaAs層(105) 、GaAlAs層(106) 
、 G a A s層(107)の3層から構成された
電流狭窄層である。
In the semiconductor element (101), (102) is a semiconductor substrate, (103) is various growth layers, (104) is between the semiconductor substrate (102) and various growth layers (103),
GaAs layer (105), GaAlAs layer (106)
This current confinement layer is composed of three layers: , Ga As layer (107).

この構成における作用を、次に説明する。The operation of this configuration will be explained next.

第1回の電流狭窄層を形成するGaAs層(105)、
GaAlAs層(106)およびGaAs層(107)
において、主に電流を狭窄する層は、GaAs層(10
7)である。G a A s N (105)は、その
上に形成される成長層(103)が、液相成長しやすい
ように設けられている。GaA1As層(106)は、
成長層(103)が成長するとき、GaAs層(107
)がその中に溶は込み成長層(103)の組成を変化さ
せることを防止する。GaAs層(105)は、そのす
べてが成長層の中に熔は込んでもその影響が生じない程
度の層厚さにしておくことが必要である。
GaAs layer (105) forming the first current confinement layer,
GaAlAs layer (106) and GaAs layer (107)
The layer that mainly constricts the current is a GaAs layer (10
7). Ga As N (105) is provided so that the growth layer (103) formed thereon can be easily grown in a liquid phase. The GaA1As layer (106) is
When the growth layer (103) grows, the GaAs layer (107)
) is infiltrated into it and prevents it from changing the composition of the grown layer (103). The thickness of the GaAs layer (105) must be such that even if all of it melts into the growth layer, no effect will be caused.

またGaA1As層(105)は、GaAs層(107
)が成長層(103)に溶は込まない程度の厚さに形成
されなければならない。このようにして本発明では、G
aAs層(107)の、成長層(103)に、対する溶
は込みが防止されるので、従来溶は込みのばらつきによ
る半導体素子の静特性や動特性の不均一性が除去され、
素子の性能、特性の均一化がはかられると共に、相異な
る導電型の層が熔は込み合って生ずる層の高抵抗化が見
られなくなり、素子の品質が向上する。
Further, the GaA1As layer (105) is the GaAs layer (107).
) must be formed to a thickness that does not melt into the growth layer (103). In this way, in the present invention, G
Since the aAs layer (107) is prevented from penetrating into the grown layer (103), the non-uniformity of the static and dynamic characteristics of the semiconductor element due to the conventional dispersion of penetration is eliminated.
The performance and characteristics of the device are made more uniform, and the high resistance of the layer, which is caused by the mixing of layers of different conductivity types, is eliminated, and the quality of the device is improved.

〔実施例〕〔Example〕

以下半導体レーザに通用した実施例に基づいてこの発明
を詳述する。なおこれによってこの発明が限定されるも
のではない。
The present invention will be described in detail below based on embodiments applicable to semiconductor lasers. Note that this invention is not limited to this.

第2図において、(1)は半導体レーザであり、(2)
はp型GaAs基板で、その上にn型GaAs層(3)
とGaA1As層(4)とGaAs層(5)からなる電
流狭窄層が形成されている。(6)はGaAs層(5)
の上に液相成長法で成長させたp型GaAlAsクラッ
ド層、(7)、 (81,(9)はさらにその上にそれ
ぞれ重ねて成長させたGaAj!As活性層、n型Ga
AJAsクラッド層、n型GaAsキャップ層である。
In Figure 2, (1) is a semiconductor laser, (2)
is a p-type GaAs substrate with an n-type GaAs layer (3) on top of it.
A current confinement layer is formed of a GaAlAs layer (4) and a GaAs layer (5). (6) is a GaAs layer (5)
(7), (81, (9)) are GaAj!As active layers grown on top of the p-type GaAlAs cladding layer grown by liquid phase growth, (7), (81, (9)) and n-type Ga
They are an AJAs cladding layer and an n-type GaAs capping layer.

この構成において、G a A s JW(5)は、p
型GaAj!Asクラッド層(6)が容部に液相成長す
るように設けられたものである。GaAl1As層(4
)は、p型GaAj2Asクラッド層(6)が成長する
とき、その中にn型GaAs層(3)が溶は込むことを
防止する。ところでGa溶液に対するGa1−xAn!
xAsの熔は込みは、Xが増大するほど減少する。従っ
て、p型GaA6Asクラッド層(6)がc a A 
s層(5)の上に成長する時、その中にGaAs層(5
)が溶は込むことがあっても、その下のGaA1As層
(4)によって、それ以上の溶は込みが防止されること
になる。
In this configuration, G a A s JW (5) is p
Type GaAj! An As cladding layer (6) is provided in the container so as to be grown in a liquid phase. GaAl1As layer (4
) prevents the n-type GaAs layer (3) from penetrating into the p-type GaAj2As cladding layer (6) when it grows. By the way, Ga1-xAn for Ga solution!
The melting of xAs decreases as X increases. Therefore, the p-type GaA6As cladding layer (6) is c a A
When growing on the s-layer (5), the GaAs layer (5) is grown on top of the s-layer (5).
) may penetrate, the underlying GaAlAs layer (4) will prevent further penetration.

ここで、n型GaAs層(3)は、電流狭窄のため、チ
ャネルの深さが1.5マイクロメ一タ程度に限定される
ため、ドナー濃度においてl X I Q ”/cd以
上、隔厚さにおいて、0.3マイクロメ一タ以上で1.
5マイクロメータ以下が必要である。また、G a A
 s 層(5)は、p型GaA7!Asクラッド層(6
)の成長時に、すべてがその中に溶は込んでもp型Ga
AJAsクラッド層(6)に対する影響が少くなるよう
に、ノンドープで、その層厚さが0.1マイクロメータ
以下であることが望ましい、 また、GaAffiAs
lW<4)は前述の溶は込み防止のためにCat−xA
xAsのXができるだけ大きい方が好ましいが、素子の
製作上からp型CaAJ!Asクラッド層(6)と同じ
であってもよい、またGaAlAs層(4)の層厚さは
溶は込み防止のためには最低0.05マイクロメータが
必要である。
Here, in the n-type GaAs layer (3), the channel depth is limited to about 1.5 micrometers due to current confinement, so the donor concentration is more than l X I Q ''/cd, and the barrier thickness is At 0.3 micrometer or more, 1.
A value of 5 micrometers or less is required. Also, G a A
The s layer (5) is p-type GaA7! As cladding layer (6
), even if all of it dissolves into it, p-type Ga
In order to reduce the influence on the AJAs cladding layer (6), it is desirable that the layer be non-doped and have a thickness of 0.1 micrometer or less.
lW<4) is Cat-xA to prevent the aforementioned melt penetration.
It is preferable that It may be the same as the As cladding layer (6), and the layer thickness of the GaAlAs layer (4) must be at least 0.05 micrometer to prevent melt penetration.

なお、半導体レーザ(1)の光の横方向の閉じ込めは、
p型GaAj!Asクラッド層(6)とGaAj?AS
層(4)のそれぞれの層厚さで決定されるので、GaA
l1As層(4)の層厚さは、必要なレーザ特性を得る
ための層厚さからp型GaAj!Asクラッド層(6)
の層厚さを差引いた値となる。
Note that the lateral confinement of the light of the semiconductor laser (1) is
p-type GaAj! As cladding layer (6) and GaAj? A.S.
Since it is determined by the thickness of each layer (4), GaA
The layer thickness of the l1As layer (4) is determined from p-type GaAj! to obtain the necessary laser characteristics. As cladding layer (6)
It is the value obtained by subtracting the layer thickness.

このようにして、この実施例における半導体レーザは、
電流狭窄層の成長層への熔は込みが防止されるので、抵
抗発熱による劣化が防止されるとともに、溶は込みのば
らつきによって生ずる性能の不均一性が除去されること
になる。
In this way, the semiconductor laser in this example is
Since melt penetration into the growth layer of the current confinement layer is prevented, deterioration due to resistance heat generation is prevented, and non-uniformity in performance caused by variations in melt penetration is eliminated.

(ハ)発明の効果 この発明によれば4.内部の電流狭窄層が成長層へ溶は
込むことが防止されるので、発熱による劣化が防止され
、溶は込み具合に影響される性能の不均一が除去されて
、寿命の長い、製作歩留りの高い半導体素子が提供され
る。
(c) Effects of the invention According to this invention, 4. Since the internal current confinement layer is prevented from penetrating into the growth layer, deterioration due to heat generation is prevented, and non-uniformity in performance affected by the degree of penetration is eliminated, resulting in a long life and production yield. A high quality semiconductor device is provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明の構成を示す構成図、第2図は、こ
の発明に係る一実施例を示す構成図である。 (ll−・−半導体レーザ、 (2)−−−−p型Ga
As基板、(3)−n型GaAs層、(41−G a 
A I A s層、(5)−G a A s層、  (
61−f)型GaAl1Asクラッド層、     (
71−G a A I A s活性層、(81−一−n
型GaAJAsクラッド層、(91−−−n型GaAs
キャップ層。
FIG. 1 is a block diagram showing the structure of the present invention, and FIG. 2 is a block diagram showing one embodiment of the present invention. (ll-・-semiconductor laser, (2)---p-type Ga
As substrate, (3)-n-type GaAs layer, (41-Ga
A I As layer, (5)-Ga As layer, (
61-f) type GaAl1As cladding layer, (
71-G a A I As active layer, (81-1-n
type GaAJAs cladding layer, (91---n type GaAs
cap layer.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板と各種成長層との間に、電流狭窄層を有
し、前記電流狭窄層がGaAs層とGaAlAs層とG
aAs層との3層から成ることを特徴とする半導体素子
1. A current confinement layer is provided between the semiconductor substrate and various growth layers, and the current confinement layer includes a GaAs layer, a GaAlAs layer, and a G
A semiconductor device comprising three layers including an aAs layer.
JP23724984A 1984-11-09 1984-11-09 Semiconductor element Pending JPS61115365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23724984A JPS61115365A (en) 1984-11-09 1984-11-09 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23724984A JPS61115365A (en) 1984-11-09 1984-11-09 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS61115365A true JPS61115365A (en) 1986-06-02

Family

ID=17012606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23724984A Pending JPS61115365A (en) 1984-11-09 1984-11-09 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS61115365A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200482A (en) * 1983-04-27 1984-11-13 Toshiba Corp Semiconductor laser device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200482A (en) * 1983-04-27 1984-11-13 Toshiba Corp Semiconductor laser device

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