JPS61115295A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make it possible to reduce the average electric power consumption without harming the advantages of bipolar type semiconductor memory, by making the structure so that the power source for only peripheral circuit is cut off when the semiconductor memory is in non-selective state. CONSTITUTION:A semiconductor memory 1 is operated by a positive power source voltage Vcc and negative power source voltae Vee. When CS is active and WE is also passive, an input data 1 is written on the memory address specified by a memory address signal AD. If CS is active but WE is passive, a data DO of the memory address specified by the address signal AD is outputted. A chip select signal SC is a signal to control a semiconductor memory 1, and if this signal CS is not inputted, namely it is passive state, the device is kept at standby state without doing read/write. Since action current is supplied only when the semiconductor memory is selected from outside, the average electric power consumption of the semiconductor memory is largely reduced.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to semiconductor memory device technology and bipolar type R
It relates to a technique that is particularly effective when applied to AM (Random Access Memory), for example.

The present invention relates to a technology that is effective for use in ECL (emitter coupled lock) type static RAM.

[Background technology]

In general, bipolar type semiconductor memory devices, particularly ECL type static RAMs, have a great advantage of high operating speed, but on the other hand, they have the problem of generally high power consumption.

Furthermore, as the power consumption is large, the amount of heat generated from the semiconductor chip is large, and for this reason, many ECL type RAMs are
In devices or systems that use heat, it becomes extremely troublesome to deal with the heat generated.

A problem arises.

In addition, regarding bipolar type RAM, for example.

"Very LSI Device Handbook" published by Science Forum Co., Ltd., November 28, 1981, 335-
It is described on page 351 etc.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device whose average power consumption can be reduced without sacrificing the advantages of bipolar semiconductor memory devices.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it is possible to cut off the power to only the peripheral circuits when the semiconductor memory device is in a non-selected state, thereby reducing the average power consumption of the bipolar semiconductor memory device without sacrificing its advantages. make it possible,
This goal is achieved.

[Embodiments] Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

Note that in one drawing, one reference numeral indicates the same or corresponding part.

FIG. 1 shows an embodiment of a semiconductor memory device according to the present invention.

A semiconductor memory device 1 shown in the figure is an ECL type high-speed static RAM, and its main part is a memory array 2.
and a peripheral circuit 3.

Although not shown, in the memory array 2, a large number of memory cells made of bipolar elements are arranged in a matrix, and a plurality of word lines and bit lines are each wired orthogonally to each other along the arrangement. has been done. This memory array 2 is connected to a first power supply circuit 4.
A holding current is supplied in an amount necessary to maintain the memory state of each memory cell. V
ccl indicates the output power supply voltage from the first power supply circuit 4.

Although not shown, the peripheral circuit 3 includes an address buffer, an address decoder, and a sense/write circuit.

Contains peripheral functions such as write/read control circuits. The peripheral circuit 3 is supplied with an operating current from the second power supply circuit 5 for operating each peripheral function. Vcc2 indicates the output power supply voltage from the second power supply circuit 5.

The semiconductor memory device 1 described above operates with the positive power supply voltage Vcc and the negative power supply voltage Vee. Also.

Its operating state is controlled by a chip select signal C8 and a write enable signal WE applied to the peripheral circuit 3. In other words, C8 is active (CS="L") and WE is active (WE="L").
”), the input data DI is written to the memory address specified by the address signal AD. Also, when C8 is active (C8=“L”) and WE is inactive (WE=”
H"), the storage data Do at the storage address specified by the address signal AD is output. The chip select signal CS is a signal that controls the operation of the semiconductor memory device 1, and this signal C8 is not input. In other words, in the inactive state (C5=''H''), the write/
A standby state is entered in which no read operation is performed.

In addition to controlling the operations described above, the chip select signal C8 is also used as a control signal to control the power supplied to the peripheral circuit 3. That is, when the chip select signal C8 becomes inactive (CS=
``l Hfi), only the operation of the second power supply circuit 5 is partially stopped, thereby substantially cutting off only the operating power supply (Vcc2) supplied to the peripheral circuit 3. A control circuit is provided.

Here, the power supply control circuit that cuts off only the power supply (Vcc2) supplied to one peripheral circuit 3 is one of the bias generation circuits 51 to 54 that supplies bias signals Vbl to Vb4 to the peripheral circuit 3, as shown in FIG. This is realized by a circuit that controls the operation.

FIG. 2 shows bias signals Vbl to Vb4 applied to the peripheral circuit 3.
Bias generating circuits 51 to 54 are shown. The bias generation circuits 51 to 54 shown in the figure are only a part of them, and each bias circuit 51 to 54 supplies a predetermined bias signal (voltage) to a large number of constant current circuits provided in the peripheral circuit 3. Give Vbl to Vb4. By controlling the operation of the bias generation circuits 51 to 54 according to the state of the chip select signal cs, the power supply ( Vcc2) can be substantially controlled.

FIG. 3 shows a first embodiment of a circuit for controlling the operation of the bias generating circuit 51. In FIG.

In the same figure, the bias generation circuit 51 is composed of an npn bipolar transistor Q1 and a resistor R2 forming an emitter follower output circuit, a resistor R1 and a constant voltage diode D1 for applying a predetermined reference voltage to the base of the bipolar transistor Ql. Ru. Transistor Q1
A constant voltage bias signal V taken out from the emitter of
bl is.

Constant current circuits 11, 12 in the peripheral circuit 3. It is distributed to I3... respectively.

Here, a circuit for controlling the operation of the bias generation circuit 51 is constituted by an npn bipolar transistor Q2 connected in parallel to the bipolar transistor Q1. A chip select signal C8 whose level has been shifted by a predetermined level by a level shift circuit 6 is applied to the base of the npn bipolar transistor Q2. Then, when the chip select signal O8 becomes inactive (C3="H"), the transistor Q2 becomes conductive and the transistor Q1 becomes conductive.
The base potential of is lowered to the negative side type g voltage Vaa side,
As a result, the bias signal Vbl is cut off. When the bias signal Vbl is cut off, the constant current flowing through each of the constant current circuits 11, 12, 13, . Become so. What should be noted at this time is that the operating current of the peripheral circuit 3 can be controlled very easily and on a small scale by using the functions of the bias generation circuit and constant current circuit without relying on power switching circuits or elements. This means that it is now possible to perform the process using only an additional configuration.

Figure 4 shows the second part of the circuit that controls the operation of the bias generation circuit.
An example is shown.

In the embodiment shown in the figure, the bipolar transistor Q2 for controlling the operation of the bias generation circuit 51 is p
An np type is used.

The fifth example shows a third embodiment of a circuit that performs OJm on the operation of a bias generation circuit.

In the embodiment shown in the figure, the circuit that controls the operation of the bias generation circuit 51 is composed of two bipolar transistors Q21.
．． It is configured using Q22. These two bipolar transistors Q21 and Q22 are connected to the chip select signal C.
Complementary conduction is driven by 8.

Figure 6 shows the fourth part of the circuit that controls the operation of the bias generation circuit.
An example is shown.

In the embodiment shown in the figure, a circuit for controlling the operation of the bias generation circuit 51 is constituted by a transistor Q2 forming a part of a constant voltage circuit in the bias generation circuit 51. In this case, the transistor Q2 is made non-active when the chip select signal O3 is in an inactive state (C5="H").

Figure 7 shows the fifth part of the circuit that controls the operation of the bias generation circuit.
An example is shown.

In the embodiment shown in the figure, the bipolar transistor Q2 in FIG. 6 is replaced with a P-channel MO8'FIi field effect transistor.

Now, in the semiconductor memory device 1 configured as above,
The peripheral circuit 3, which accounts for a large proportion of its total power consumption, has a chip select signal C8 in an active state (cs=”
The operating current flows only when the voltage is low (L"), that is, only when the semiconductor memory device 1 is selected from the outside.

This makes it possible to significantly reduce the average power consumption of the semiconductor memory device 1 as a whole.

Further, as the average power consumption is reduced, the amount of heat generated from the semiconductor chip is also reduced, which greatly facilitates heat generation in a device or system using a large number of semiconductor memory devices. Furthermore, by controlling the operating power supply to the peripheral circuit 3 indirectly via the bias generation circuits 51 to 54, the configuration for the control is
It can be obtained by very simple additional construction without using power switching circuits or elements.

〔effect〕

(1) By cutting off the power to only the peripheral circuits when the semiconductor memory device is in a non-selected state, the average power consumption of the bipolar semiconductor memory device can be reduced without sacrificing the advantages of the bipolar semiconductor memory device. I can do it. This effect can be obtained.

(2) In addition, with the reduction in average power consumption, the amount of heat generated from the semiconductor chip also decreases, which has the effect of greatly simplifying heat generation in devices or systems that use a large number of semiconductor memory devices. can get.

(3) Furthermore, by controlling the operating power supply to the peripheral circuits indirectly via the bias generation circuit, the configuration for the control can be made very simple without relying on power switching circuits or elements. can be obtained by simple additional construction.

This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

In the above description, the invention made by the present inventor was mainly applied to an ECL type high-speed static RAM, which is the field of application in which the invention was made, but the invention is not limited thereto.

For example, it can be applied to a programmable ROM. It can be applied at least to conditions where the operation is controlled by a chip select signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a configuration for controlling operating power supplied to peripheral circuits, and FIG. 3 is a block diagram showing an embodiment of a configuration for controlling the operating power supplied to peripheral circuits. times, to control the operation of the circuit! ,)□1 piece, oh,,1 Figure 4 shows the second part of the circuit that controls the operation of the bias generation circuit.
FIG. 5 is a diagram showing an embodiment, and FIG.
Figure 6 shows the fourth embodiment of the circuit that controls the operation of the bias generation circuit.
FIG. 7 is a diagram showing an embodiment of the present invention, and FIG.
It is a figure showing an example. 1... Semiconductor storage device, 2... Memory array, 3
... Peripheral circuit, 4... First power supply circuit that supplies a holding current to the memory array, 5... Second power supply circuit that supplies operating current to the peripheral circuit, 51 to 54... Bias generation circuit , 6... Level shift circuit, Vcc... Positive side power supply voltage, Vee... Negative side power supply voltage, cs... Chip select signal, WE... Write enable signal.
DI data input, DO...data output, AD...address signal, Vbl~Vb4...bias signal, 11
゜I2, 13... Constant current circuit, Q2... Power supply control circuit (transistor). Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A semiconductor memory device whose operation is controlled by a chip select signal, and a power supply control circuit that cuts off only the power supplied to peripheral circuits when the chip select signal is in an inactive state. A semiconductor storage device characterized by having a built-in. 2. The power supply control circuit indirectly controls only the power supplied to the peripheral circuit by controlling the operation of a bias generation circuit that supplies a bias signal to the peripheral circuit. A semiconductor memory device according to claim 1.