JPS6348694A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To quicken the read speed further by using a bipolar transistor (TR) so as to discharge a data line used in common between plural cell blocks. CONSTITUTION:Bipolar TRs Q7, Q8 discharge data lines DL, the inverse of DL. A bipolar TR has a far larger current capability in comparison with a MOS TR of nearly the same size and a current of the TR Q9 as a current source is selected comparatively largely and the size of the TRs Q7, Q8 is formed comparatively largely while not so much limited as a MOS TR in a memory cell. Thus, the discharge of the data line DL is conducted in a short period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory constructed by combining a bipolar transistor and a complementary insulated gate transistor. That is, the present invention relates to a semiconductor memory having a Bi-CMO8 configuration.

[Conventional technology]

By taking advantage of both the high speed of bipolar transistors and the low power consumption and high integration ratio of C'MO8) transistors, static semiconductor memory 'J (SRAM) with Bi-CMO8 configuration was developed (Nikkei) Electronics March 1, 1986 issue pI), 199-21
7). This Bi-CMO8SRA~1 is an address buffer and a decoder driver.

The sense amplifier, output circuit, etc. have a Bi-CMO8 configuration,
By making the memory cell array section particularly n-MOS p, it is possible to achieve high speed and CM similar to bipolar memory.
It has low power consumption and large storage capacity (high integration!fJ') comparable to OS memory.

[Problem that the invention seeks to solve]

However, even such Bi-CMO8SRAM is still insufficient in its high-speed read operation. One of the major reasons for this is that the charge on the common data line is discharged by a MOS transistor in the memory cell. In other words, as is the case with the above Bi-CMO8SRAM,
Generally in SRAM.

M) A large number of memory cells arranged in an IJ wax pattern are divided into a plurality of cell blocks, and a pair of output terminals of each cell block are commonly connected to a pair of common data lines. Alternatively, a predetermined number of all cell blocks are each commonly connected to one pair of the plurality of pairs of common data lines. Each cell block includes a plurality of word lines, a pair of bit lines, a plurality of memory cells connected to one word line and a pair of bit lines, and a gate connected between the pair of bit lines and a common data line. It has a pair of transistors for receiving a bit line selection signal. Therefore, the charge on the common data line is transferred to the bit line by the MOS transistor in the aE memory cell.
Discharged through the OS transistor. As the storage capacity increases, the bit lines and common data lines become longer and the parasitic capacitance (on the other hand, the MOS in the memory cell) increases.
The transistor becomes finer as its storage capacity increases, and its current capacity decreases because the 1L voltage of the power supply does not change.

Therefore, it takes time to discharge the common data line, and this is one of the major reasons for limiting the improvement in the read speed of B i -CN I O8 SRAM.

Therefore, an object of the present invention is to provide a Bl-CMO8SRAM having a configuration that further improves the readout speed.

Another object of the present invention is to provide a new data writing and reading method due to the new configuration.

[Means for solving problems]

A semiconductor memory according to the present invention includes a word line, a pair of bit lines, a memory cell connected to the word lines and a pair of bit lines, a pair of data lines, and a base of one of the data lines connected to the other. Bipolar type first and second transistors whose other bases are respectively connected to and whose collector-emitter current paths are connected in series between the pair of data 131, and the terminals of these transistors M1 and iM2 are connected to a common connection point. a third transistor connected to receive a column selection signal, the first or second transistor and the third transistor connected to each other;
a sense amplifier that amplifies the potential difference between the data lines caused by conduction with the transistor; and a sense amplifier that generates a potential difference between the data lines in response to the data signal to be written and transfers the potential difference between the collector and base of the first and second transistors. It includes at least a data write circuit for transmitting data to the bit line pair via the junction.

As described above, in the semiconductor memory according to the present invention, the data line is discharged by the bipolar transistor, and not by the small MOS transistor in the memory cell as in the conventional example. Since bipolar transistors have much greater current capability than MOS transistors of similar size, the discharge time constant of the data line is reduced, further improving the read speed. Because a bipolar transistor is used, in a data write operation, a potential difference is forcibly generated between the data lines in response to the data signal to be written, and that potential difference is transferred to the bit line pair via the collector-base junction of the bipolar transistor. and controls the data stored in the memory cells.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory showing one embodiment of the present invention. Generally, in a static semiconductor memory, a large number of semiconductor memory cells are arranged in rows and columns p to form a memory cell array, and are further divided into cell blocks of a predetermined number. The figure shows only one memory cell MC. This memory cell consists of four N-channel MO8) transistors Q
t, Qz, Qs and Q, and two P-channel MOS
has transistors Q3 and Q4, and transistor Q+
Q4 to Q4 are connected in a flip-flop type, and transistors Qs and Q6 function as transfer gates. Transistor Q3. A resistor may be used instead of Q4.

Memory cell Mc is connected to a word line WL and a pair of bit lines BL and BL. Bi,,h1g! BL and BL are connected to power supply terminal Vcc via resistors R1 and R3, respectively. Resistor "M" instead of "l5R3"
OS) transistors may be used.

B+7) lines BL and BL are connected to the bases of bipolar NPN transistors Q7 and Qa, respectively, provided according to the invention. These transistors Q
7. The collector-emitter current paths of Qs are connected in series between the data lines DL and DL, as shown in FIG. 1, so that their collectors form a pair of data lines DL and L)L. The common connection point for the 9 transistors and Qs is M
Grounded through the OS transistor Q9, its
A column selection signal Y is supplied. A bipolar type device may be used as an all-transistor Q group. A pair of data HDLs
, DLn, Bi-CMO 8m configuration (D sense amplifier and output circuit 11, and data input and write circuit 12 of 13i-C'540S configuration).

Ru.

With reference to FIGS. 2 and 3, let us explain the data recording C output operation and the data write operation, respectively.

In the data read operation, the 5th row address human power cat 1-1
Valid row address signals RA0 to RAi supplied to 1 to 1-i are supplied to the row address decoder/driver 7 via the row address buffer 6, and as a result, the word scarlet selection signal X1 goes to the selection level (high level). 0 row address signals RA0 to R that are inverted and the word line WL is activated
When Ai is other information, one of the other selection signals X2 to Xm is set to the selection level and other word lines are activated.

Buffer 6 and decoder driver 7 are Bi-CMO
3 configuration, the word line W1 is energized as follows.

As shown in Figure 2, the process ends within a short time from the address capture point.

Transfer gate transistors Qs and Q in memory cell MC
s is thus conductive. Data @1 in memory cell MC
Since 1 has been written, transistors Q2 and Q3 are in a conductive state. therefore.

Bit line BL is discharged by transistor Q via transistor Q6. Since the bit line BL or BL is discharged by the MOS transistor, the same bit line pair BL
, BL is connected to a large number of memory cells MC, the discharge time constant becomes very large. Therefore, it is more effective to reduce the number of memory cells connected to the same bit line pair.

A countermeasure to this is to increase the number of cell blocks connected to the same data line pair DL and DL to lengthen the data line, but since the data line is discharged by a bipolar transistor, the discharge time constant Kanashi can be made smaller. This will be explained in detail later.

On the other hand, the valid column address signals CAo to CAj supplied to the first column address terminals 2-1 to 2-jVC are Bi-CMO.
Bi-CMO 8 via column address buffer 8 with 8 configurations.
The transistor Qs is taken into the column address decoder/driver 9 of the configuration, and as a result, the one column selection signal Y1 changes to a high level in a short time, and the transistor Qs becomes conductive. Column address decoder/driver 9rOi sets one of the signals Y3 to Ym to a selection level in accordance with other column address information. The conduction of transistor Qsrt causes transistor Q7 to
It acts as a current source for Qa, and at this point the base potential of transistor Q7 is higher than that of Qa. Therefore, transistor Qγ becomes conductive, and data line D
Discharge the charge of L. A pair of data lines DL and DLK
can be shared among multiple cell blocks due to its large storage capacity,
Further, as described above, the number of cell blocks increases as the number of memory cells connected to the pair of bit lines BL, BL in each cell block decreases. That is, the data lines DL, DL are not long and their capacitance is relatively large.

For this reason, when the data myJIi is discharged by a small transistor in the memory cell as in the conventional Bi-CMOS S RAM, the discharge time constant becomes very large, as indicated by the dotted line 50 in FIG. As such, the data line DLld is slowly discharged.

This limits the improvement in read speed. In the present invention, the data line DL(f)L) is released by the bipolar transistor Qa(Qs). Bipolar transistors have a much larger current capacity than MOS transistors of similar size.

In addition, the current value of the transistor Q as a current source can be set relatively large, and the transistors Q y , Q
The size of the MoS transistor in the memory cell is not limited and can be made relatively large. therefore.

The data line DL is released in a short time as shown in FIG.

In the data read operation, since the read/write signal WE supplied to the terminal 3 is at the read level (low level), the control circuit 10 sets the read activation signal WE to a high level and sets the write activation signal Ei to a low level. Therefore, sense amplifier and output circuit 11 is activated, while data input and write circuit 12 is in an inactive state.

Thus, the sense amplifier and output circuit 11 having the Bi-CMO8 configuration amplifies the potential difference between the data line pair DL, DL, and generates the output data DOυ of '11 at the output terminal 4. 2nd in time
The time is TL in the figure. On the other hand, in the conventional example, since the discharge time constant of the data line DL is large, its access time is set to Tn.

Note that the bit line pair BL, BL caused by data reading
The potential difference between the data line pair 1) and the potential difference between L and DL is set to an intermediate level without setting the source 4 voltage.

Improves operating speed.

In the data write mode, up to the activation of the word line W is the same as in the data read mode. If the selected memory cell MC stores data 11'', the potential of the bit line BL is lowered by the transistor Q2.

At the time of data writing, signals 4i to VB to terminal 3 take the no-y level, and therefore the write activation signal WE goes to the high level. This signal WEd is also supplied to the column address decoder/driver 9. Therefore, even when the column address signals CAo to CAj are received, the first column address decoder driver 9 holds the column selection signal Y1 at a low level and maintains the cut-off state of the transistor Q, as shown in FIG. Instead, the first column address decoder/driver 9 supplies a high-level signal Yl/ to the data input and write circuit 12, and connects the data line pair DL, DLK-) connected to the data input and write circuit 12 to the data input and write circuit 12. The circuit 12 is informed that the memory cell is the target of data writing. Note that if there is only one pair of data lines DL, DL, it is not necessary to generate the signals Y, /. The data input and write circuit 12 thus forces one of the data lines DL and DL to a low level in response to the write data DIN supplied to the input terminal 5. When writing data "Ol", data NDL is inverted to low level. At this time, transistors Q and Qs are in a cut-off state. Therefore, the bit @BL at high level is between the collector base of transistor Qy. as shown in Figure 3. Since the data line DL is at a high level, the PN junction between the collector and base of the transistor Qy is reverse biased. When the voltage becomes lower than that, transistors Qs and Q4 become conductive, and Qh and Qs are cut off.This state is maintained even if the data input and write circuit 12 sets the potential of both data lines DL and DL to a high level. This is because the collector-base junctions of transistors Qy, Q- are reverse biased.

〔Effect of the invention〕

Based on the above, the present invention uses several bipolar transistors as data lines that are commonly used among a plurality of cell blocks, and because of this structure, the selected memory is We provide a Bi-CMO8 SRAM that further improves the read speed by writing data into cells.

[Brief explanation of drawings]

FIG. 1 is a professional diagram showing an embodiment of the present invention. FIG. 2 is a timing chart for a data read operation, and FIG. 3 is a timing chart for a data write operation. Agent Patent Attorney FF3 Original Head 'No.
1 rise 2 kunime 3 sentences

Claims (1)

[Claims] A word line, a pair of bit lines, a memory cell connected to the word line and the bit line, a pair of data lines, and a collector emitter with one base connected to one of the pair of data lines and the other base connected to the other. A bipolar type first current path is connected in series between the pair of data lines.
and a second transistor, a third transistor connected to a common emitter connection point of these first and second transistors and receiving a column selection signal, caused by conduction between the first or second transistor and the third transistor. a sense amplifier that amplifies the potential difference between the data lines; and a sense amplifier that generates a potential difference between the data lines in response to a data signal to be written, and applies the potential difference to the collector-base PN junction of the first and second transistors. A semiconductor memory comprising at least a data write circuit for transmitting data between the bit lines.