JP2792675B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a two-port memory device having a random access memory (RAM) array and a serial access memory (SAM) array therein. is there.

[Conventional technology]

In recent years, a two-port memory device for application to a graphic display system has been proposed. This two-port memory device has a randomly accessible RAM
It has an array and a serially accessible SAM array, and performs an operation of simultaneously transferring a plurality of data in parallel between the two arrays. For details, see Nikkei Electronics Magazine 19
It is shown in the August 12, 1985 issue (pp. 211-240).

 The configuration of this conventional example will be described below.

FIG. 2 is a circuit diagram showing a SAM array and a RAM array of a conventional two-port memory, and a connection portion thereof. In FIG. 2, reference numeral 1 denotes a SAM array, 2 denotes a RAM array, and both arrays 1 and 2.
2 are connected by a plurality of data line pairs including a first data line 3 and a second data line 4. The SAM array 1 includes a plurality of first memory cells 7 arranged in a row and a plurality of control lines 10-1 and 10-2.
Memory cells 7 are cross-coupled to each other in the first
A CMOS inverter 11 and a second CMOS inverter 12;
, And a second MOS transistor 14. The input terminal of the first CMOS inverter 11 and the output terminal of the second CMOS inverter 12 (hereinafter referred to as node 1) are connected to the drain of the first MOS transistor 13 and An output terminal,
The input terminal of the second CMOS inverter 12 is connected to the drain of the second MOS transistor 14 (this is called node 2), and the gates of the first and second MOS transistors 13, 14 are connected to the control line 10-. First, the sources are the first and second
Are connected to the data lines 3 and 4. The power supply terminals of the first CMOS inverter 11 and the second CMOS inverter 12 are directly connected to the common power supply line 5, and the ground terminal is directly connected to the common ground line 6.

On the other hand, the RAM array 2 includes a plurality of second memory cells 17 arranged in a grid and a plurality of sense amplifiers 21 connected to the data line pairs 3 and 4, and an equalizing circuit also connected to the data line pairs 3 and 4. 22, and a plurality of word lines 20-1, 20-2,
20-k, each second memory cell 17 is constituted by a transfer gate 18 and a memory cell capacitor 19 connected to the source of the transfer gate 18, and the gate of the transfer gate 18 is connected to the word line 20 _-1 . At any one of 20- _x , the drain is connected to the first or second data line 3,4. The first and second data lines 3 and 4 each have a parasitic capacitance 23.

Next, a method of transferring data from the RAM array 2 to the SAM array 1 will be described with reference to FIG. First, the equalizing circuit 22 equalizes the first data line 3 and the second data line 4 to the 1/2 Vcc level. Subsequently, one of the word lines, for example, the word line 20-1 is set to the H level,
The transfer gate 18 in the memory cell 17 to which the word line is connected is opened, and the charge of the memory cell capacitor 19 is stored in the corresponding first cell.
To the data line 3 of FIG. Here, assuming that the H level is stored in the memory cell capacitance, the potential of the first data line 3 increases from 1 / 2Vcc to 1 / 2Vcc + ΔV by reading, and the potential of the second data line 4 becomes 1 / Vcc. It remains at 2 Vcc.
Subsequently, the sense amplifier 21 is activated, charges and discharges the charge of the parasitic capacitance 23 of the first and second data lines, amplifies the potential difference,
When the amplification is sufficiently performed, the first data line 3 goes high and the second data line 4 goes low. Subsequently, one or more of the control lines, for example, the control line 10-1 is started up, the first and second MOS transistors 13 and 14 are turned on, and the data of the data line pair 3 and 4 is stored in the memory. Write to cell 7. At this time, if the data stored in the memory cell 7 is that the node 1 (24) is at the L level and the node 2 (25)
Is at the H level, the data at node 1 is inverted from L to H, and the data at node 2 is inverted from H to L. The transfer for inverting the data in the memory cell 7 in this manner is hereinafter referred to as inversion transport.

[Problems to be solved by the invention]

The problem of the conventional semiconductor memory device is described in the first section.
3 will be described with reference to FIG. In the figure, before the inversion transfer, the first data line 3 is at the H level, the second data line 4 is at the L level,
The node 1 (24) is at the L level and the node 2 (25) is at the H level. In this state, Nch.Tr2 (31) and Pch.Tr1 (32)
ON. Set the control line 10 to H and set the first and second MO
When the S transistors 13 and 14 are turned on, a current flows from the first data line 3 to the node 1 (24) and from the node 2 (25) to the second data line 4, and the node 1 changes from the L level to the intermediate potential. , The node 2 changes from the H level to the intermediate potential. Therefore Nc
h.Tr1 (30), Nch.Tr2 (31), Pch.Tr1 (32), Pch.Tr2 (3
Since 3) is all in the ON state, Pc
h.Tr2 (33) and Nch.Tr2 (31) to the common ground wiring 6 and from the common power supply wiring 5 to Pch.Tr1 (32) and Nch.Tr1
Through current flows to the common ground 6 via (30). Therefore, when there are a large number of first memory cells performing the inversion transfer, a large current flows during the transfer. Further, the first data line 3
Charges supplied to the node 1 (24) from Nch.Tr1 and Nch.Tr
The electric charge discharged from the common ground line 6 to the ground via the second line 2 and extracted from the node 2 (25) by the second data line 4 is supplied from the power supply through the common power supply line and the Pch.Tr1 and Pch.Tr2. Since the second data line 4 is charged, both the node 1 (24) and the node 2 (25) try to keep the intermediate potential, and it is difficult to perform quick data inversion transfer.

Therefore, in the configuration of the conventional semiconductor memory device, when the number of inversion transfers is increased, the through current and the power consumption at the time of transfer become large values, and further, there is a problem that data inversion transfer is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a semiconductor memory device capable of easily performing data inversion transfer while reducing through current and power consumption during transfer. .

[Means for solving the problem]

In the semiconductor memory device according to the present invention, a load element is inserted between a current wiring and a common power supply wiring in a SAM array, or between a ground wiring and a common ground wiring in a SAM array.

[Action]

In the present invention, the load element is inserted between the power supply wiring and the common power supply wiring in the SAM array or between the ground wiring and the common ground wiring in the SAM array. Since the potential drops below the power supply potential level and the ground wiring in the SAM array rises above the ground potential level,
Construct a memory cell (first memory cell) in the array
Nch.Tr1, Nch.Tr2, Pch.Tr1, Pch.Tr2 are hard to turn on.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 1 is a first memory array corresponding to a SAM array, 2 is a second memory array corresponding to a RAM array, and 3 , 4 are first and second data lines, respectively, which are connected to each other between the first and second memory arrays 1 and 2 in pairs. Reference numerals 5 and 6 denote a common power supply wiring and a common ground wiring common to the entire chip, to which a power supply potential and a ground potential are applied, respectively. Reference numeral 7 denotes first memory cells arranged in a row in the first memory array 1, and reference numerals 8 and 9 denote power supply wirings in the array and ground wirings in the array, respectively, all of the first memory cells in the first memory array 1. Are connected in common to the memory cells. Reference numeral 10 denotes a control line which is connected to the gates of the first and second MOS transistors 13 and 14 and controls the conduction state of the first and second MOS transistors. Reference numerals 11 and 12 denote first and second inverters, respectively. The input terminal of the first inverter 11, the output terminal of the second inverter 12, and the drain of the first MOS transistor 13 are connected at a node 1 (24). , The output terminal of the first inverter 11, the input terminal of the second inverter 12, and the drain of the second MOS transistor 14 are connected to the node 2 (2
Connected in 5). Further, a first load element 15 is connected between the array power supply wiring 8 and the common power supply wiring 5, or a second load element 16 is connected between the array ground wiring 9 and the common ground wiring 6. Also, the second memory array 2 includes a plurality of second memory cells 17 arranged in a lattice, each of the second memory cells 17 having a means 26 for storing information, Means 27 for outputting to line pairs 3 and 4.

Next, the operation of the above embodiment will be described with reference to FIG. 1 and FIG. 4 in which the first memory array portion of FIG. 1 is enlarged.

In this embodiment, load resistors having a higher resistance value than the main wiring are used as the load elements 15 and 16 and N
ch.Tr1 (30), Nch.Tr2 (31), Pch.Tr1 (32), Pch.Tr1
A CMOS inverter consisting of (33) is used. (4th
First, in FIG. 1, the information stored in the information storage means 26 of the plurality of second memory cells 17 of the second memory array 2 is converted into a plurality of data line pairs 3, 4 by using the information output means 27. Output to Representative examples of the information storage means 26 and the information output means 27 include the means described in the conventional example.

In FIG. 4, the H level is applied to the first data line 3-1.
When the L level is output to the second data line 4-1 and the node 1 of 24-1 is at L level and the node 2 of 25-1 is at H level, inversion transfer is performed in the memory cell 7-1. . When the control line 10-1 rises, the first and second MOS transistors 13-1, 14-1 ... 13-m, 14-m are simultaneously turned on. Then, in the first memory cell 7-1, the first MOS transistor 13-1, the node 1 (24-1), the Nch. Tr2 (31), the ground line 9 in the array,
A current path can be made to the ground via the load resistor 16 and the common ground wiring 6. With this current path, the potential of the ground wiring 9 in the array rises above the ground potential (L level).

First and second MOS transistors 13-1, 14-1 ... 13-m, 14
Since −m is turned on at the same time, data transfer is performed by m second memory cells 7-1,..., 7-m, of which m ′ second memory cells are simultaneously subjected to inversion transfer. In this case, a large current of m 'times tends to flow through the load resistor 16, so that the potential of the ground wire 9 in the array rises above the L level. Similarly, power supply wiring 8 in the array
Is at the power supply level (H level) by the load resistor 15.
Greater drop. Therefore, Nch.Tr1 (30), Nch.Tr2
(31), the potential difference between the source and the gate, and the potential between the source and the drain of each transistor of Pch.Tr1 (32) and Pch.Tr2 (33) becomes small, and each transistor becomes difficult to turn on. Therefore, from the common power supply wiring 5 to the load resistance 15, the power supply wiring 8 in the array, Pch.T
r2 (33), Nch. Tr2 (31), ground wiring 9 in the array, to the ground via the load resistance 16, and from the common power supply wiring 5 to the load resistance 15, power supply wiring 8 in the array, Pch. Tr1 (32), Nch.Tr1
(30), the through current flowing to the ground via the array ground wiring 9 and the load resistor 16 is suppressed. Further, the current from the first data line 3-1 to the node 1 (24-1) immediately charges the node 1 (24-1), and the node 2 (25-
Since the current from 1) to the second data line 4-1 immediately discharges the node 2 (25-1), the inversion transfer is easily performed.

FIG. 5 is a circuit diagram showing a main part of another embodiment of the present invention. In this embodiment, a Pch. Load transistor 15 is used as a first load element, an Nch. Load transistor 16 is used as a second load element, and load transistor control lines 34 and 35 are added to control the load transistor. It is a thing. Other parts are the same as those of the above embodiment.

Only the difference between the data transfer method and the embodiment will be described. During data transfer, control line 10-1 is set to H
At the same time, the Pch. Load transistor control line 34 rises from L to H, and the Nch. Load transistor control line 35 falls from H to L. Then, the resistance values of the load transistors 15 and 16 become extremely high only at the time of data transfer, and the through current at the time of transfer is almost completely cut off. Therefore, Nch.Tr1 (30), Nch.Tr2 (31),
Since the Pch.Tr1 (32) and the Pch.Tr2 (33) are almost completely kept in the OFF state, the inversion transfer becomes very easy and the through current and power consumption at the time of the transfer can be greatly reduced.

〔The invention's effect〕

As described above, according to the present invention, the load element is provided between the power supply wiring in the SAM array and the common power supply wiring, or between the ground wiring and the common ground wiring in the SAM array. In this case, there is an effect that a through current and a power consumption at the time of transferring a plurality of data from the memory to the SAM array at the same time can be reduced, and the inversion transfer can be easily performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional semiconductor memory device, FIG. 3 is an enlarged view of a main part of FIG. 2, and FIG. Is the first
FIG. 5 is an enlarged view of a main part of the drawing, and FIG. 5 is a circuit diagram showing a semiconductor memory device according to another embodiment of the present invention. In the figure, 1 is a first memory array, 2 is a second memory array, 3 is a first data line, 4 is a second data line, 5
Is a common power supply line, 6 is a common ground line, 7 is a first memory cell, 8 is an array power line, 9 is an array ground line, 10-1 and 10-2 are control lines, and 11 is a first inverter. , 12 is a second inverter, 13 is a first MOS transistor, 14 is a second MOS transistor, 15 is a first load element, 16 is a second load element, 17 is a second memory cell,
24 is a node 1, 25 is a node 2, 26 is an information storage means, and 27 is an information output means. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A first memory array, a second memory array, a plurality of data line pairs connected between the memory arrays, a common power supply line for providing a power supply potential, and a common ground line for providing a ground potential. Wherein each of the data line pairs comprises a first data line and a second data line having complementary signals, and wherein the first memory array comprises a plurality of first memory cells; An array power supply line, an array ground line, and a control line, wherein the first memory cell includes first and second inverters, and first and second MOS transistors, respectively. The input terminal of the first inverter and the output terminal of the second inverter are both connected to the drain of the first MOS transistor, and the output terminal of the first inverter and the output terminal of the second inverter. The power terminals are both connected to the drain of the second MOS transistor, the power terminals of the first and second inverters are connected to the power supply line in the array, and the ground terminals of the first and second inverters Are connected to the ground wiring in the array, the gates of the first and second MOS transistors are connected to the control line, and the sources of the first and second MOS transistors are the first and second MOS transistors. The power supply wiring in the array and the ground wiring in the array are connected in common to all the first memory cells in the first memory array, and the control line is connected to the A first power supply connected in common to a plurality of the first memory cells in one memory array, and a main power supply between the power supply wiring in the array and the common power supply wiring A first load element having a higher resistance than a line, or a second load element having a higher resistance than a main ground wiring is connected between the in-array ground wiring and the common ground wiring; Comprises a plurality of second memory cells, wherein the second memory cells store information;
Means for outputting the stored information to the plurality of data line pairs.