JPS61114618A - Exclusive or circuit - Google Patents

Abstract

PURPOSE:To decrease the number of elements by constituting the titled circuit that the 1st (2nd) switch element is conductive when the applied voltage to the 2nd (1st) input terminal is in the 1st level and the 3rd (4th) switch element is conductive when the applied voltage to the 2nd (1st) input terminal is in the 2nd level. CONSTITUTION:A binary signal is fed to input terminals 1, 2. A switch 4 is inserted between the input terminal 1 and an output terminal 3, the element 4 is opened when a voltage B at the input terminal 2 is at a high level and closed when at a low level. A switch element 5 is opened when a voltage A at the input terminal 1 is at a high level and closed when at a low level. Switch elements 6, 7 are connected in series between the output terminal 3 and command and the switching of the elements 6, 7 is controlled respectively by the voltage B, A. When the voltages A, B are both at a low or a high level, the potential of the output terminal 3 is at a low level. Then when the voltage A is at a high level and the voltage B is at a low level, or vice versa, the potential of the output terminal 3 goes to a high level in both cases. Thus, an exclusive OR signal EXOR of voltage signals fed to the terminals 1, 2 is outputted to the output terminal 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an exclusive OR circuit, and particularly to an exclusive OR circuit improved to reduce the number of elements.

[Prior Art] FIG. 2 is a logic diagram showing an example of a conventional exclusive OR circuit. FIG. 2 is an example of a circuit in which the logic circuit shown in FIG. 1 is configured with 0MO8. As shown in the figure, when the conventional exclusive OR circuit is configured with 0MO8, a total of 1
Requires 0 transistors.

[Problems to be solved by the invention] As mentioned above, the conventional exclusive OR circuit requires many transistors, which increases the area occupied on the semiconductor substrate. The drawback was that it could not be used effectively. This drawback is particularly noticeable in electronic circuits that use a large number of such exclusive OR circuits.

Furthermore, the conventional exclusive OR circuit requires a large number of transistors, which has the disadvantage of slowing down the calculation speed.

This invention was made to solve the above-mentioned problems, and can be configured with a small number of transistors, which occupies less space on a semiconductor substrate, and can perform exclusive OR operations at high speed. The purpose of this invention is to provide an exclusive OR circuit that allows

[Means for Solving the Problems] The present invention connects a first switch element whose conduction is controlled by a voltage applied to a second input terminal between a first input terminal and an output terminal. , a second switch element whose conduction is controlled by the voltage applied to the first input terminal is connected between the second input terminal and the output terminal, and a third switch element whose conduction is controlled by the voltage applied to the first input terminal is connected between the output terminal and the ground. A fourth switch element is connected in series and inserted, the conduction of the third switch element is controlled by the voltage applied to the second input terminal, and the conduction of the fourth switch element is controlled by the voltage applied to the first input terminal. It is controlled by the voltage applied.

[Function] The first switch element conducts when the voltage applied to the second input terminal is at the first level, and the second switch element conducts when the voltage applied to the first input terminal is at the first level. The third switch element conducts when the voltage applied to the second input terminal is at the second level, and the fourth switch element conducts when the voltage applied to the first input terminal is at the second level. Conducts when the level is .

[Embodiment] FIG. 4 is a circuit diagram for explaining the present invention in detail. In the figure, a binary voltage of high level and low level is applied to the first input terminal 1. In such a logic circuit, one of the binary voltages is defined as logic "1" and the other is defined as logic rOJ. Similarly, the second
A binary voltage of high level and low level is also applied to the input terminal 2 of . A first switch element 4 is inserted between the first input terminal 1 and the output terminal 3. This first
The opening and closing of the switching element 4 is controlled by the voltage applied to the second input terminal 2.

That is, the first switch element 4 is opened when the voltage B is at a high level, and closed when the voltage B is at a low level. Second
A second switch element 5 is inserted between the input terminal 2 and the output terminal 3 of. The opening and closing of this second switch element 5 is controlled by the voltage A applied to the first input terminal 1. That is, the second switch element 5
It is opened when is at a high level and closed when is at a low level. A third switch element 6 and a fourth switch element 7 are connected in series and inserted between the output terminal 3 and the ground. The opening and closing of the third switch element 6 and the fourth switch element 7 are controlled by voltage B and voltage A, respectively.

That is, the third switch element 6 is closed when the voltage B is at a high level, and is opened when the voltage B is at a low level. Fourth
The switching element 7 is closed when the voltage A is at a high level, and is opened when the voltage A is at a low level.

The operation of the above configuration will be explained. First, when voltages A and B are both low level, the first and second switch elements 4 and 5 are closed, the third and fourth switch elements 6 and 7 are opened, and the output terminal 3
The potential of becomes low level. Next, when voltage A is high level and voltage B is low level, the first . Third switch elements 4 and 6 are closed, second and fourth switch elements 5 and 7 are opened, and the potential at output terminal 3 becomes high level. Next, when the voltage B is at a low level and the voltage B is at a high level, the second and fourth switch elements 58 and 7 are closed, and the first and third switch elements 4 and 5 are closed.
and 6 are opened and the output terminal; (The potential of child 3 becomes high level. Next, voltages A and B
When both are at high level, the third and fourth switching elements 6 and 7 are closed, the first and second switching elements 4 and 5 are opened, and the potential of the output terminal 3 becomes low level. Therefore, the exclusive OR signal EXOR of the voltage signals applied to the first input terminal 1 and the second input terminal 2 is output to the output terminal 3.

As described above, in the circuit shown in FIG. 4, the exclusive OR circuit is configured with four switch elements, so the number of required elements is significantly smaller than that of the conventional exclusive OR circuit. Although any switch element that performs the above-described operation can be used as the switch element, FIG. 1 shows an embodiment in which a field effect transistor is used.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, this embodiment uses n-channel transistors 40 and 50 as the first and second switch elements 4 and 5 shown in FIG. 7
0 is used. And each control wl! of the first transistor 40 and the third transistor 60! The pole is connected to the second input terminal 2. In addition, the second transistor 5o
and each control electrode of the fourth transistor 70 is connected to the first input terminal 1.

FIG. 5 is a waveform diagram for explaining the operation of the circuit of FIG. 1. The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG. Note that in this embodiment, the high level voltage applied to the first and second input terminals 1 and 2 is
V and the low level voltage is OV. As shown, the voltage A applied to the first input terminal 1 and the second
When the voltages B applied to the input terminals 2 of are all at low level (OV) or both at high level (5■), the potential at the output terminal 3 is at low level.

Further, when one of the voltages A and B is at a high level and the other is at a low level, the potential of the output terminal 3 is at a high level. Therefore, an exclusive OR signal EXOR of voltages A and B is output to output terminal 3.

Comparing the circuit of the embodiment shown in FIG. 1 explained above and the conventional exclusive OR circuit shown in FIG. The number can be reduced by about 60%. Roughly speaking, the calculation speed is about 30% faster than conventional circuits.
% can be shortened.

By the way, in the embodiment shown in FIG. 1, when voltages A and B are both low level, the first and second transistors 40 and 50 are both conductive, and the third and fourth transistors are conductive.
transistor 60. t5 and 70 become non-conductive, and a low level potential should appear at the output terminal 3.

However, due to the threshold voltages of the p-channel transistors 40 and 50, the potential EXOR appearing at the output terminal 3 is higher than 0■ by the threshold voltage ■rH. Therefore, the circuit shown in FIG. 1 has the problem that the output voltage may not be completely Ov depending on the combination of input logics, and there is room for rough improvement.

FIG. 6 is a circuit diagram showing another embodiment of the present invention which has been improved to solve the problems of the embodiment of FIG. 1 as described above. In the figure, in this embodiment, a parallel transistor 400 is used as the first switch element,
A parallel transistor 500 is used as the second switch element.

The parallel transistor 400 is configured by connecting a p-channel transistor 400a and an n″ff Jannel transistor 400b in parallel.p-channel transistor 400
The second input terminal 2 is connected to the control electrode a. n
A fourth input terminal 9 is connected to the control electrode of the channel transistor 400b. This fourth input terminal 9 has
A voltage with a polarity inverted from the voltage B applied to the second input terminal 2 is applied. On the other hand, the parallel transistor 500 has a configuration in which a p-channel transistor 500a and an n-channel transistor 500b are connected in parallel. p
The first input terminal 1 is connected to the control electrode of the channel transistor 500a.

Further, the third input terminal 8 is connected to the control electrode of the n-channel transistor 500b. A voltage having a polarity inverted from the voltage A applied to the first input terminal 1 is applied to the third input terminal 8 .

Next, the operation of the embodiment shown in FIG. 6 will be explained. The operation of this embodiment is mostly similar to the operation of the embodiment shown in FIG. 1, so only the operation when a problem occurs in the embodiment shown in FIG. 1 will be described. That is, when voltages A and B are both low level, p-channel transistor 400a
, n-channel transistor 400b, El channel transistor 500a, 15, and n-channel transistor 500b are all in a conductive state, and the third t3 and fourth transistors eo1'3 and 70 are in a non-conductive state. In this case, p-channel transistor 40
The threshold voltage VrH occurring at 0a and 500a is n
This is canceled out by channel transistors 400b and 500b, and a voltage of Ov appears at output terminal 3 as shown in FIG. Therefore, although the number of transistors is slightly increased in the embodiment of FIG. 6, the problems of the embodiment of FIG. 1 can be completely solved.

Note that the embodiments described above use MO as the switch element.
Although the description has been made using an S transistor, as described above, any switch element may be used as long as it performs the operation as described in FIG. 4.

[Effects of the Invention] As described above, according to the present invention, a circuit can be configured with a significantly smaller number of switch elements than in the past, and exclusive logic can be used to perform rough calculations at a higher speed than in the past. A summation circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Second
The figure is a logic diagram showing an example of a conventional exclusive OR circuit. The third factor is a circuit example in which the logic circuit shown in diagram N1 is configured with 0MO8. The fourth factor is a circuit diagram for explaining the invention in detail. FIG. 5 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1. FIG. 6 is a circuit diagram showing another embodiment of the invention. The seventh factor is a waveform diagram for explaining the operation of the embodiment shown in FIG. In the figure, 1 is a first input terminal, 2 is a second input terminal, 3 is an output terminal, 4 is a first switch element, 5 is a second switch element, 6 is a third switch element, and 7 is a a fourth switch element, 8 a third input terminal, 9 a fourth input terminal, 4o a first transistor, 50 a second transistor, 60 a third transistor, 70 a fourth transistor, 400 and 500 are parallel transistors, 40
0a and 500a are n-channel transistors, 400
b and 500b indicate n-channel transistors.

Claims (3)

[Claims] (1) A first input terminal to which binary voltages of a first level and a second level are applied; and a second input terminal to which binary voltages of the first level and a second level are applied. , an output terminal; connected between the first input terminal and the output terminal;
and a first switch element that is conductive when the voltage applied to the second input terminal is at a first level, and connected between the second input terminal and the output terminal,
and a second switching element that is conductive when the voltage applied to the first input terminal is at a first level, one end of which is connected to the output terminal, and a voltage applied to the second input terminal. a third switch element that is conductive when is at a second level; and a third switch element that is connected between the other end of the third switch element and ground, and that the voltage applied to the first input terminal is at a second level. and a fourth switch element that is conductive when the level is high. (2) The first to fourth switch elements are configured with field effect transistors having control electrodes, and the first switch element is configured to operate under a p-channel electric field with the second input terminal connected to the control electrode. an effect transistor, the second switch element includes a p-channel field effect transistor having a control electrode connected to the first input terminal, and the third switch element has a control electrode connected to the second input terminal. The fourth switch element includes an n-channel field effect transistor connected to an input terminal thereof, and the fourth switch element includes an n-channel field effect transistor whose control electrode is connected to the first input terminal. The exclusive OR circuit described in item 1. (3) a third input terminal to which a binary voltage is applied that is complementary to the voltage applied to the first input terminal; and a third input terminal that is complementary to the voltage applied to the second input terminal. a fourth input terminal to which a related binary voltage is applied; the first to fourth switch elements are configured of field effect transistors having control electrodes; a p-channel field effect transistor whose control electrode is connected to the second input terminal; and a p-channel field effect transistor whose control electrode is connected to the fourth input terminal.
The second switch element includes a p-channel field effect transistor whose control electrode is connected to the first input terminal, and a p-channel field effect transistor whose control electrode is connected to the third input terminal. terminal connected n
configured in parallel connection with a channel field effect transistor, the third switch element includes an n-channel field effect transistor whose control electrode is connected to the second input terminal, and the fourth switch element includes: 2. The exclusive OR circuit according to claim 1, comprising an n-channel field effect transistor having a control electrode connected to said first input terminal.