GB2089160A - Programmable logic gates & networks - Google Patents

Abstract

The network connections of the channels of complementary symmetry MOS FET's (P11, N11) in a logic gate or array are electrically alterable, by gate injection MOS FET's (P12, N12),to program different logic responses to logic inputs. To enable an input (IN1) P12 is made a depletion device (normally ON), and N12 enhancement (normally off). To disable an input, P12 is made enhancement, N12 depletion. Fets N19, N29, N39 allow gate-source (or drain) programming voltages to be applied to the serially connected (N-channel) devices. <IMAGE>

Description

SPECIFICATION Programmable logic gates & networks This invention relates to programmable logic gates and networks.

Programmable arrays of logic gates are known in which the gates are connected by fusible links, which connections can be severed by passing currents much higher than those encountered when switching at normal logic levels through the fusible links to melt them away. Once programmed, these logic arrays generally cannot be re-programmed.

Electrically alterable programable logic arrays using gate-injection non-volatile memory metal-axidesemiconductor (GIMOS) field effect transistors (FET's) are known. The threshold voltage (VT) which must be applied between the source and gate of such a device to condition it for conduction between its source and drain can be changed responsive to higher-than-normal voltages applied between its gate and its source or drain. GIMOS FET's as devices are described in U.S. Pat. No.4, 162,504 issued 24July 1979 to S.T. Hsu and entitled "FLOATING GATE SOLID-STATE STORAGE DEVICE," the type of GIMOS FET described therein having a floating gate structure that does not overlap either of its source and drain regions and is disposed under the normal gate electrode, and in U.S. Pat. Application Serial No. 181,662 filed 26August 1980 by S.T.

Hsu and entitled "ELECTRICALLY PROGRAMMABLE, FLOATING GATE READ ONLY MEMORY DEVICE AND METHOD FOR MAKING SAME", also in our UK application No. 7932557, the types of GIMOS FET described therein having a floating gate which overlaps one and only one of its source and drain regions and is disposed under the normal gate electrode. Logic arrays constructed with these devices have heretofore employed FET's of one conductivity type in their construction.

In logic networks, which are not programmable and use FET's with fixed VT'5, it has been found that complementary symmetry MOS FET's provide savings in standby power consumption. Each COSMOS pair, comprising a p-channel FET and an n-channel FET serially disposed between a pair of supply voltage terminals, can be made with transistors that are not only of complementary conductivity types, but also have V;s which are of the same amplitude, giving a high degree of noise immunity to logic circuits incorporating them.

The present invention permits the extension of these advantages to programmable logic gates and to networks of these gates in connection with each other.

In the present invention, the electrical network connections of the channels of COSMOS FET pairs which would define a conventional logic gate or array are modified in accordance with the invention to include in proper disposition the channels of programmable-threshold voltage FET's, which programmable-thresholdvoltage FET's are switched into conduction or non-conduction during a programming interval by application of programming voltages between their gates and ends of their channels. Thereafter, until re-programmed, these programmable-threshold-voltage FET's retain their conductive or non-conductive conditions to control the logic response of the logic gate or array.

In the drawing: Figure 1 is a schematic diagram of a programmable logic gate embodying the invention; Figure 2 is a schematic diagram of a variant of the Figure 1 programmable logic gate, also embodying the invention; Figure 3 is a schematic diagram of a variant of the Figure 2 programmable logic gate, also embodying the invention; Figures 4, Sand 6 are respectively: a schematic diagram of a non-programmable COSMOS logic network, a schematic diagram of a portion of a programmable logic network generated from the Figure 4 logic network, and a schematic diagram of a programmable logic network derived by a reduction process from the Figure 5 network and embodying the invention, which series of figures illustrates the process for designing such logic networks; and Figure 7 is a schematic diagram of a variant of the Figure 6 programmable logic network, also embodying the invention.

Referring to Figure 1, p-channel FET's P11, P21, P31 and n-channel FET's N11, N21, N31, N19, N29, N39 shown with single gate structures are MOS FET's with fixed VETS. PI 1, P21, P31 have their gates interconnected at terminals IN 1, 1 N2, 1N3, respectively, with the gates of Nil, N21, N31, respectively, to form respective COSMOS pairs i.e., the devices all have similar amplitude Vets. The devices are enhancementmode types with the VT/S of the p-channel devices being negative and the VT/S of the n-channel devices being positive, as measured from source to gate.The relatively positive and relatively negative operating voltages V+ and V- applied to terminals V+ and V- differ by an amount substantially less than this VT, SO that when the interconnected gates of the p-channel and n-channel devices in the COSMOS pair are swiched to one of the operating voltages V+ and V- only one of the devices will be conditioned to conduct. This essentially eliminates stand-by power consumption, and the COSMOS pairs draw appreciable power from the operating voltage supplies only when switching.

P-channel FET's P12, P22, P32 and n-channel FET's N12, N22, N32 are shown with further, respective floating gate structures in addition to their wired gate structures and are GIMOS FET's as described in the previously noted U. S. Pat. No.4,162,504. Application between the source and gate of one of the n-channel GIMOS FET's N12, N22, N32 of a progamming source-to-gate voltage that is positive in polarity and much larger in amplitude than (V+)-(V-)will alter the charge stored between its channel and floating gate such that, until it is re-programmed, the FET responds to normal logic levels with behaviour typical of a depletion-mode device, its channel being fully conductive for any source-to-gate potential (or VGS) in a range including zero and all positive values.That is, the n-channel GIMOS FET behaves like a short-circuit between its source and drain for the operating voltages encountered during normal logic operation.

On the other hand, application of a sufficiently large negative programming source-to-gate potential between the source and gate of this n-channel GIMOS FET will alter the charge stored between its channel and floating gate to cause it to respond to normal logic levels with behavior like that of an enhancement-mode FET with a VT substantially larger than (V+)-(V-). That is, the n-channel GIMOS FET behaves like an open-circuit between its source and drain for the operating voltages encountered during normal logic operation.

Analogously, a p-channel GIMOS FET can be programmed to operate as a short-circuit between source and drain after being programmed with a negative source-to-gate voltage of amplitude substantially larger than (+V)-(-V) applied between source and gate, or to operate as an open-circuit between source and drain after being programmed with a sufficiently large positive source-to-gate voltage applied between source and gate. (The GIMOS FET's described in U. S. Pat. No.4,162,504 are bilateral devices so far as common-gate connection is concerned, and their programming can be carried out equally well by applying programming voltages as drain-to-gate voltages instead of or as well as source-to-gate voltages.) In Figure 1 a write decoder WD responds to a 3-bit binary number to program the GIMOS FETs within the following constraints.The p-channel of P11 is a short-circuit if the n-channel of N11 is an open-circuit, and conversely is an open-circuit if the n-channel of N1 1 is a short-circuit. The p-channel of P21 is a short circuit if the n-channel of N21 is an open-circuit, and conversely is an open-circuit if the n-channel of N21 is a short-circuit. The p-channel of P31 is a short circuit if the n-channel of N31 is an open-circuit, and conversely is an open-circuit if the n-channel of N31 is a short-circuit. The p-channel and n-channel GIMOS FET's can be so constructed that the same programming voltage can be simultaneously applied to those bearing identification alphanumerics having identical numerical portions, so that two-conductor programmingvoltage buses B1, B2 and B3 can be replaced by respective single-conductor buses, at least in part.The programming voltages from write decoderWD are presumed to be referenced with respect to a ground potential intermediate between V- and V+.

The source electrodes of p-channel GIMOS FET's P12, P22, P32 connect to the positive supply voltage rail running from terminal V+, so the application of source-to-gate programming voltages to them is straightforwardly accomplished by applying to their gates the voltages as referred to ground. The source electrode of n-channel GIMOS FET N12 connects to the negative supply voltage rail running from terminal V-, so the application of course-to-gate programming voltage to it is straightforwardly accomplished also by changing gate voltage. Problems arise, however, when one attempts to apply programming voltage to the gate of one of the n-channel GIMOS FETs N22 or N32 inasmuch as neither end of its channel is referred to ground, V- or V+ potential.N-channel FET N1 9 with source connected to receive V- responds to a positive-logic "high" or "one" (i.e., a negative-logic "low" or "zero") applied to its gate to apply V- potential to the interconnected drain of N12 and source of N22, to permit source-to-gate voltage programming of N22 (as well as drain-to-gate voltage programming of N12). N-channel FET N29 with source connected to receive V- responds to a positive-logic "high" or "one" applied to its gate to apply V- potential to the interconnected drain of N22 and source of N32, to permit source-to-gate voltage programming of N32 or drain-to-gate voltage programming of N22. N-channel FET N39 with source connected to receive Vresponds to a positive-logic "high" or "one" applied to its gate to apply V- potential to the drain of N32 to permit drain-to-gate voltage programming of N32.The positive-logic "high" or "one" is applied simultaneously to the gates of N19, N29, N39 via a terminal WRITE. In certain logic configurations it may be desirable to reverse the order of the serial connection of the GIMOS and fixed-VT FET's as between terminal +V and OUT, causing a problem of applying programming voltages to the GIMOS FET similar to that encountered when programming N22 and N32; the solution to the problem is analogous to that used for solving the problem with programing N22 and N32, with a P-channel fixed-VT FET being activated to short one of the ends of the channel of the GIMOS FET to terminal V+.

The clamping of otherwise unreferenced nodes during programming may be viewed as the reconnection of portions of the circuitry during programming such that: all the channels of the programmable-VT p-channel FET's therein are paralleled with each other with at least first ends of their channels connected to a point of reference voltage (e.g., V+) against which the programming voltages applied to their respective gates can be referred, and all the channels of the programmable-VT n-channel FET's therein are paralleled with each other with at least the first ends of their channels connected to a point of reference voltage (e.g., V-) against which the programming voltage applied to their respective gates can be referred. In taking such a view one must be careful to exclude from such connections the circuitry connecting directly to the logic output terminal OUT, if the reference voltages against which the p-channel and n-channel programmab le-VT FET's are respectively programmed differ. This is necessary to prevent the introduction of an undesired short between these reference voltages during programming.In more complex programmable logic arrays, as will be described further on in this specification, particularly those constructed from stand-cell semiconductor layout and specialized metalization patterns, it may be convenient to program with the V+ and V- terminals connected to a common voltage during programming and arrange for clamping of all circuit nodes to that common voltage -- in effect, paralleling the channels of all programmable-VT FET's.

The transistors which are used to clamp otherwise unreferenced nodes during programming should be large enough devices to conduct, without coming out of tight voltage clamp, the currents that flow in the channels of the GIMOS FET's being programmed. There generally is no need for these clamp transistors to operate at high speed, so their large size is acceptable. One attactive feature of the programmable logic of the invention is that the programming voltage sources and the source applying voltage to terminal WRITE all supply FET gates, so the loading in them and the buses they supply is small. This permits the use of polycrystalline-silicon for these buses, supposing the programmable logic gate to be monolithically integrated on the surface of bulk silicon or of silicon-on-sapphire.

The Figure 1 circuit will by analogy to known COSMOS logic gates be a 3-input NAND gate for positive-logic input signals applied to its three input terminals IN1, IN2, and IN3 and taken from its output terminal OUT, or a 3-input NOR gate for negative logic signals, providing that the programming has conditioned the GIMOS FET's as follows. P-channel GIMOS FET's P12, P22, P32 are programmed to short-circuit the sources of fixed-VT p-channel FET's P11, P21, P31 to terminal V+; and n-channel GIMOS FET's N12, N22, N32 are programmed to be open-circuits across the channels of fixed --VT n-channel FET's N1 1, N21, N31, respectively.If one and only one of the p-channel GIMOS FET's P12, P22, P32 is programmed as an open-circuit rather than short-circuit and if the n-channel GIMOS FET having the same first digit in the numeral portion of its identification alphanumeric is programmed as a short-circuit, the Figure 1 circuit will by analogy to known COSMOS logic gates be a 2-input NAND gate for positive-logic signals applied to two of its input terminals and will be non-responsive to signal applied to the other of its input terminals.If two of the p-channel GIMOS FET's P12, P22, P32 are programmed as open-circuits and the n-channel GIMOS FET's having corresponding first digits in the numerical portions of their identification alphanumerics are programmed as short-circuits, the Figure 1 circuit will be analogous to a simple COSMOS inverter, inverting logic signals applied to one of its input terminals and being non-responsive to logic signals applied to either or both of its other input terminals. The positive-logic logic equations respectively describing the responses T1, T2, T3, T4, T, T6, T7, T8 at terminal OUT to input logic signals Ii, 12, 13 applied to terminals 1N1, 1N2, 1N3, respectively, are tabulated below, together with the conditions of the GIMOS FET's for generating such responses.

PROGRAMMING CODE SHORT-CIRCUIT OPEN-CIRCUIT LOGIC V12-V22-V32 GIMOS FET's GIMOS FET's EQUATION 000 P12,P22,P32 N12,N22,N32 T0=11.12.l3 001 P12,P22,N32 N12,N22,P32 T1=11.12 010 P12,N22,P32 N12,P22,N32 T2=11.13 011 P12,N22,N32 N12,P22,P32 T3=lX 100 N12,P22,P32 P12,N22,N32 T4=12. 13 101 N12,P22,N32 P12,N22,P32 T5=12 110 N12,N22,P32 P12,P22,N32 T6=13 111 N12,N22,N32 P12,P22,P32 T7=0 The logic equations above and in the remainder of this specification are written using the normal conventions wherein the logical complement of a signal is indicated by over-scoring it with a bar, wherein the AND function is indicated by a dot product symbol and wherein the OR function is indicated by a + sign.

The "programming code" in the left hand column of the table above described (in "high" and "low" terms expressed as "one" and "zero", respectively) the program voltages applied to cause the transistor conduction characteristics shown in the middle columns of the table. V12 is the voltage applied to the gates of P12 and N12; V22 is the voltage applied to the gates of P22 and N22 and V32 is the voltage applied to the gates of P21 and N32.

Figure 2 shows the Figure 1 programmable logic gate modified so that programming voltages are applied via the same lines used for conducting logic signals, as is often done in prior art programmable logic arrays.

Figure 3 shows a modification of the Figure 2 logic gate wherein each series connection of a fixed -VT FET and a GIMOS FET with floating gate disposed symmetrically over the channel between its source and drain regions is replaced by its electrical equivalent, a single GIMOS FETwith floating gate asymmetrically disposed over the channel between its source and drain regions to overlap just one of these regions as described in the afore-mentioned applications, with the overlapped region being the source. Homologs of the Figures 1,2 and 3 programmable logic gates, wherein p-channel FET's are replaced by n-channel FET's of corresponding types and wherein supply voltage polarities are reversed to suit so as to form positive-logic NOR gates or negative-logic NAND gates, are, of course, possible.

Those familiar with COSMOS logic design know that an array of individual NAND and NOR gates interconnected in parallel cascade connections can usually be reduced to a simpler connection in which the NAND and NOR functions are no longer separable into individual collections of devices. The invention is applicable to such logic arrays, as well as to a single plural-input programmable logic gate. To describe the procedure for doing this in a general context is difficult and cumbersome, so a specific example of the designing of such a network will be described, which should enable a logic designer of ordinary skill to practice the invention in such arrays.

First, a general logic equation known from experience to be of sufficient complexity to provide for all desired programming alternatives must be selected. As the specific example, let us assume the following logic equation to be the selected general logic equation.

Th=w71 . Wl5)+W5 4)] The form of the logic equation with inputs all barred or "low" to cause the output to be "high" indicates to one familiar with COSMOS logic design that with all the inputs low the equivalent non-programmable COSMOS logic array should have a high-conductance network between terminals V'+ and OUT and have a high-impedance network between terminals OUT and V'-. The high-conductance network would comprise p-channel FET's switched to short-circuit condition, and the high-impedance network would comprise n-channel FET's switched to open-circuit condition. The logic equation is bracketed somewhat unusually so that every term is ANDed or ORed with a term bearing a brace of the same order; this is done to simplify the application of the following rules.For high-conductance networks the AND terms of a logic equation signify series connections of short-circuit switch elements; and the OR terms, parallel connections of short-circuit switch elements. For high-impedance networks, on the other hand, the AND terms of a logic equation signify parallel connections of open-circuit switch elements; and the OR terms, series connections of open-circuit switch elements.

Applying the first of these rules to the selected general logic equation, the ANDing ofT4 and i5 requires a series connection of the conductive p-channels of FET's P41 and P51 in the conventional unprogramable COSMOS logic array shown in Figure 4. The ORing ofW5) with (i5 . i4) requires the parallelling of the p-channel of FET P61 with this series connection. The ANDing of the [(i6) + (15 . 4)] logic term associated with the resulting parallel-series circuit and of the [i7] logic term requires that the parallel-series circuit be in series connection with the p-channel a further FET P71.The gates of P41, P51, P61, P71 connect to input terminals IN4, IN5, IN6, IN7 respectively for receiving the input positive-logic signals b, 15, l, 17 respectively, which control their respective conduction.

Applying the second of these rules to the selected general logic equation, the ANDing ofT4 and 15 requires a parallel connection of the non-conductive n-channels of FET's N41 and N51. The ORing ofW5) with .

requires the series connection of the n-channel of FET N61 with this parallel connection. The ANDing of the [W5)+ W5 . 14)] logic term associated with the resulting series-parallel circuit and of theW7] logic term requires the series-parallel connection be parallelled by the n-channel of a further FET N71. The gates of N41, N51, N61, N71 connect to input terminals IN4, IN5, IN6, IN7 respectively for receiving the input positive-logic signals 14,15,16,17 which control their respective conduction.

Figure 5 show the first step to be taken to convert the non-programmable logic network of Figure 4 into a programmable logic array in accordance with the invention. The respective switches for short-circuiting all circuit nodes to supply during the programming of the array are omitted for clarity. The series and parallel connections of transistors to be described following are, more precisely, series and parallel connections of their conduction channels unless otherwise specifically described.

The NAND and NOR gates described with the aid of Figures 1,2 and 3 are a degenerate form of the general class of networks now being described, and one may be misled by looking at them into believing the rule for constructing more elaborate switching networks is to insert in series with each parallelly connected logic FET a GIMOS FET of similar conductivity type and in parallel with each serially connected logic FET a GIMOS FET of similar conductivity type, and to connect the gates of the GIMOS FET pairs similarly to the pairs of logic FET's which they control. The actual rule is somewhat more complex.

The GIMOS FETs are not associated with just the logic FET's on a corresponding basis, but rather are associated on a corresponding basis with both the logic FET's and the network branches in which they are located. This leads to the following three rules for generating the programmable logic array from the COSMOS circuit used to realize the most complex logic equation.

RULE I: Each logic FET and parallel combination ofcircuit branches that is in series with a logic FET or parallel combination of circuit branches should be paralleled by a GIMOS for programming purposes.

RULE II: Each logic FET and series combination ofcircuit branches that is to be in parallel connection with a logic FET or series combination of circuit branches should be serially connected with a GIMOS FETfor programming and the resulting series connections paralleled instead.

RULE Ill: The gates of the GIMOS FET's that are duals, insofar as admittance and impedance in their respective networks selectively connecting terminal OUT to respective ones of V+ and V- terminals are concerned, are connected together to receive programming voltage on the same line.

In converting Figure 4 into Figure 5 according to these rules, P41 and P51 are each in series connection with another FET (i.e., each other), so are paralleled by p-channel GIMOS FET's P42 and P52 respectively.

N41 and N51 are each in parallel connection with another FET (i.e., each other), so are put into series connection with p-channel GIMOS FET's N42 and N52, respectively, which series connections are then paralleled. P42 and N42 are duals, P42 being a series impedance element and N42 a parallel conductance element, so their gates are interconnected to the same programming line running to terminal PR4. Similarly, P52 and N52 are duals and their gates are interconnected to the same programming line and to terminals PR5.

The series connection of P41 and P51 in Figure 4 is in parallel connection with FET P61 calling into operation Rule II, that instructs the insertion of a p-channel GIMOS FET 82 in series with the series connection of P41 and P51 and the insertion of a p-channel GIMOS FET 62 in series with FET P61, in Figure 5.

The parallel connection of N41 and N51 in Figure 4 is in series connection with FET N61 so according to Rule I n-channel GIMOS FET N82 is parallelled with the parallel connection and n-channel GIMOS FET N62 is parallelled with N61. P62 and N62 are duals so their gates are interconnected to the same programming line and to terminal PR6. P82 and N82 are duals with gates connection to terminal PR8.

P71 is in series with the parallel connection of the other p-channel FET's described above, so they are paralleled with p-channel GIMOS FET's P72 and P92, respectively. In Figure 4, N71 parallels the serial connection of the other n-channel FET's described above, so they are serially connected in Figure 5 with n-channel GIMOS FET's N72 and N92, respectively, before being paralleled. P72 and N72 are duals with gates connected to terminal PR7, and P92 and N92 are duals with gates connected to terminal PR9.

As thus far described, the programmable logic array requires six programming lines accessed by programming terminals PR4, PR5, PR6, PR7, PR8 and PR9. It is desirable to reduce the number of programming lines required in an array -- if possible, to the same number as there are logic input terminals, so the programming lines may be accessed through the logic input terminals without need for separate programming terminals. A first step is to look for programing redundancies; and sometimes, particularly in simpler arrays, this can be done by inspection. Looking at FigureS, for example, it is clear P92 and N92 are superfluous. The short-circuiting provided by P92 can be carried out by P42, P52 and P82 being simultaneously conductive. The open-circuiting provided by N92 can be carried out by N42, N52 and N82 being simultaneously non-conductive.

Some thought will lead one to the conclusion that the superfluity of P92 and N92 illustrates that RULES I and II for generating the programmed logic array are a little more general than need be. There are two corollaries to RULES I and II, following, which, if simultaneously applied, avoid the need for subsequent reduction of the logic array.

COROLLARY TO RULE I: Rule I is not applied for series connections of a plurality of parallel combinations.

COROLLARY TO RULE II: Rule II is not applied for parallel connections of a plurality of serial combinations.

The second step in reduction of the number of lines for programing the network is made reflective of the reasons that P82 and N82 had to be inserted into the Figure 5 network. P82 is inserted to avoid short-circuiting the branch containing P61, P62 when P42 and P52 are both programmed conductive; and N82 is inserted to avoid open-circuiting the source of N61 when N42 and N52 are both programmed to be non-conductive.The programming condition that causes difficulty is the application of "lows" to the interconnected gates of P42, N42 and to the interconnected gates of P52, N52. If P82 could be replaced by a programmable logic gate that would be rendered non-conductive for only this programming condition, and if N82 could be replaced by a programmable logic gate that would be rendered conductive for only this programming condition, these two logic gates replacing P82 and N82 could be programmed from the same lines as P42, N42 and P52, N52. A programmable OR gate in negative-logic -- i.e., two paralleled n-channel GIMOS FET's N84 and N85 --is the suitable replacement for P82.A programmable AND gate in negative-logic--i.e., two serially connected p-channel GIMOS FET's P84 and P85 -- is the suitable replacement for N82.

Figure 6 shows the resulting programmable logic network, with the programming lines brought out to terminals PR4, PR5, PR6, PR7 in Figure 4 now brought out to logic input terminals IN4, IN5, IN6, IN7 instead.

During programming, p-channel FET's P49, P59, P69, P79 clamp the nodes, to which their drains respectively connect, to V'+ terminal responsive to a voltage pulse applied to terminal WRITE'. This pulse is negative respective to the voltage at terminal V+ by an amount greater than the VT'S of P49, P59, P69, P79. During programming, n-channel FET's N89 and N99 clamp the nodes to which their drains respectively connect to V'-terminal responsive to a voltage pulse applied to terminal WRITE'. This pulse is positive-going respective to the voltage at terminal V'- by an amount greater the the VTBS of N89, N99. Figure 7 shows the Figure 6 programmable logic network modified to replace N41 and N42 by a single n-channel FET N43 with one long wired gate and one short floating gate, to replace N51 and N52 by a single n-channel FET N53 with one long wired gate and one short floating gate, to replace P61 and P62 by a single p-channel FET P63 with one long wired gate and one short floating gate, and to replace N71 and N72 by a single n-channel FET N73 with one long wired gate and one short floating gate.

The programmable logic available from the logic networks of Figures 6 and 7 is tabulated below. The programming code comprises V42, V52, V62 and2 as bits. V42, V52, V62 and V72 are the programming voltages applied respectively to IN4, IN5, IN6 and IN7 logic input terminals, "One" in the programming code indicates the previous respective programming voltage V42, V52 or V72 was "low"; "zero," in the programming code indicates that such programming voltage was "high". In the case of V62 a "one" in the programming code indicates the previous programming voltage was "high"; "zero", that it was "low".

PROGRAMMING CODE SHORT-CIRCUIT OPEN-CIRCUIT LOGIC V42-V52-V62-V72 GIMOS FET's GIMOS FET's EQUATION 0000 N42,N52,P62,N72 P42,P52,N62,P72, T0=I7+ [I6.(I5+I4)] N84,N85 P84,P85 0001 N42,N52,P62,P72, P42,P52,N62,N72 T1 =I5.(15+14) N84,N85 P84,P85 0010 N42,N52,N62,N72 P42,P52,P62,P72 T2= 17+15+14 N84,N85 P84,P85 0011 N42,N52,N62,P72 P42,P52,P62,N72 T3=I5+l4 N84,N85 P84,P85 0100 N42,P52,P62,N72 P42,N52,N62,P72 T4=I7+(I6.I4) N84,P85 P84,N85 0101 N42,P52,P62,P72 P42,N52,N62,N72 T5=1614 N84,P85 P84,N85 0110 N42,P52,N62,N72 P42,N52,P62,P72 T6=17+14 N84,P85 P84,N85 0111 N42,P52,N62,P72 P42,N52,P62,N72 T7=I4 N84,P85 P84,N85 1000 P42,N52,P62,N72, N42,P52,N62,P72 T8=I7+(I6-I5) P84,N85 N84,P85 1001 P42,N52,P62,P72 N42,P52,N62,N72 T9=(I6-I5) P84,N85 N84,P85 1010 P42,N52,N62,N72 N42,P52,P62,P72 T10=I7+l5 P84,N85 N84,P85 1011 P42,N52,N62,P72 N42,P52,P62,N72 T11=I5 P94,N85 N84,P85 1100 P42,P52,P62,N72 N42,N52,N62,P72 T12=17+16 P84,P85 N84,N85 1101 P42,P52,P62,P72 N42,N52,N62,N72 T13=i6 P84,P85 N84,N85 1110 P42,P52,N62,N72 N42,N52,P62,P72 T14=j7 P84,P85 N84,N85 1111 P42,P52,N62,P72 N42,N52,P62,N72 T15=0 P84, P85 N84, N85 If one skilled in the art of logic design examines the various programmed logic statements that can be derived from To, he will be provided with the experience necessary to select a To of sufficient generality to obtain all programmed logic statements he requires. In summary, To should be chosen such that omission of selected logic inputs from To will generate all logic statements one desires to program.

The principles set forth in connection with the design of the Figures 6 and 7 programmable logic networks can be extended to still more complex programmable logic networks, there being an increase in the complexity of the programmable logic gates used to prevent the simultaneous programming-out of a plurality of unwanted logic variables also incidentally and undesirably programming-out a wanted logic variable, of course.

Attention is directed to several matters regarding the programmable OR gate comprising n-channel GIMOS FET's N84 and N85. First, note that these GIMOS FET's (although operated as logic, rather than linear, devices) are operated in source-follower mode. Ordinarily, non-programmable FET's in COSMOS logic circuitry are not operated in source follower mode, because the source-to-gate offset voltage (VGS), which must be maintained to keep each of the enhancement-mode FET's conductive, keeps the transistor source from being clamped to the drain, (and consequently prevents the logic output terminal from being pulled to the supply voltage).However, the GIMOS FET's of the described OR gate, when programmed for conduction, are conditioned to operate in depletion-mode, with the floating gate potentials of N84 and N85 remaining, after programming for conduction, much more positive than the positive supply voltage at terminal V+. As a consequence, the source of N84 and N85 can be clamped to their drains.

The clamping available when the field effect devices are depletion mode can be exploited in another way in the programmable logic gates and networks. It permits the channels of an n-channel and p-channel pair of programmable VT FET's with interconnected gates to be exchanged in position within the network. Such exchange affects programmability of the network, in that the polarity of the programming voltage applied to achieve a certain program must be reversed. In addition,the V'+ and V'- voltages tend to buck (instead of aid) the programming voltage, so that amplitude of the programming voltage may need to be increased.

However, where two different logic outputs are to be simultaneously programmed from shared input terminals or programming lines, this technique can be usefully employed.

Note that in any of the circuitry thus far described the tight clamping of source and drain voltages in the GIMOS FET's when they are programmed for conduction is advantageously used. It is this property which keeps the programmable-conduction devices from inserting offset voltages that would interfere with the complementary symmetry of the conduction characteristics of the fixed-VT logic FET's. The programmable VT GIMOS FET's introduce no substantial change into the noise immunity properties of COSMOS logic gates or arrays.That is, the intermediate voltage levels at which the p-channel and n-channel COSMOS FET's exchange principal conduction role is not substantially affected by the programmable-VT FET's, so complementary symmetry of conduction characteristics can be maintained by proved semiconductor manufacturing processes.

The other unusual thing about the OR-gate connection of FET's N84 and N85 is that it is a programmable switch that solely of itself performs a logic function on the programming instructions, being programmable responsive to a plurality of inputs, rather than a single input. This programmable switch is useful, not only in programmable logic arrays, but in other circuitry as well. For example, these programmable switches may be used to replace simpler FET switches in current mirror amplifiers with current gains programmed by selective connections through switches, as described in U. S. Patent No. 4,064,506 issued to J. M. Cartwright, Jr., 20 December 1977 and entitled 'CURRENT MiRROR AMPLIFIERS WITH PROGRAMMABLE CURRENT GAINS." These switches can be used to control arithmetic operations (multiplying, dividing, root-taking, raising to a power, etc.) carried out using the logarithmic properties of bipolar transistors, too, as a further example of their use.

In the following claims, while the FET's are individually claimed, it is intended that the claims include within their scope those situations where two FET's share channel and wired-gate structures.

Claims (7)

1. A logic gate having: first and second supply voltage terminals; an output terminal selectively connected to said first supply voltage terminal through a first series connection of the principal current conduction paths of a plurality of transistors of a first conductivity type, and selectively connected to said second supply voltage terminal through the principal current conduction paths of each of like-numbered plurality of transistors of a second conductivity type complementary to the first; a plurality of input terminals each connected to the control electrodes of a respective one of each of said plurality of transistors; and, for electrically programming the logic response of said gate:: at least one pair of transistors each having electrically programmable threshold voltage between a control electrode thereof and one of the two electrodes defining the ends of its principal current conduction path, the first transistor of each pair having its principal current conduction path connected in a parallel connection with one of said plurality of transistors of first conductivity type and the second transistor of each pair having its principal current conduction path included in a respective further series connection between said output terminal and said second supply voltage terminal, which respective further series connection is with the principal current conduction path of that one of the said plurality of transistors of said second conductivity type having its control electrode connected to the same input terminal as the control electrode of the transistor of first conductivity type with principal current conduction path connected in parallel with that of the first transistor of that pair.

2. A logic gate as set forth in claim 1 including electrically controlled voltage clamps responsive to a WRITE signal to selectively clamp to one of said first and second supply terminals at least one of the ends of the principal conduction paths of transistors which are electrically programmable but have neither end of their conduction paths directly connected to either of the first and second supply voltage terminals.

3. A logic gate as set forth in claim 2 wherein respective transistors of each pair have electrically programmable electrical conduction paths of said first and second conductivity types and have control electrodes connected together.

4. A logic gate as set forth in claim 3 wherein the control electrodes of each pair of transistors with electrically programmable threshold voltages have their control electrodes connected to a respective one of said input terminals.

5. A logic gate as set forth in claim 4 further including: a further input terminal; a pair of further complementary-conductivity transistors with fixed threshold voltage and a pair of further complementary conductivity transistors with electrically programmable threshold voltage, all having control electrodes connected to said further input terminal, the principal current conduction paths of those transistors which are of first conductivity type in series connection between said first supply voltage terminal and said output terminal, the principal current conduction paths of these transistors which are of second conductivity type in a further parallel connection which further parallel connection is included common in each of said further series connections;; still further transistors of said first conductivity type, with electrically programmable threshold voltages, with gate electrodes each connected to the same input terminal as the gate electrode of a respective corresponding one of the transistors of second conductivity type and with programmable threshold voltage in a respective further series connection, and with principal current conduction paths in a still further series connection paralleling those portions of said further series connections exclusive of said second parallel connection; and still further transistors of said second conductivity type, with electrically programmable threshold voltages, with gate electrodes each connected to the same input terminal as the gate electrode of a respective corresponding one of the transistors in said first series connection, and with principal current conduction paths in a still further parallel connection included in said first series connection.

6. A programmable electric network formed from connections of non-programmable elements and programmable-conduction switch elements selectively connecting a respective pair of nodes, said switch element being programmably responsive to a plurality of programming voltage bits and said programmable conductive elements comprising a plurality of programmable-threshold-voltage transistors connected as a logic gate for programming instructions with respective gate electrodes for receiving respective ones of said programming voltage bits and with respective channels through selected ones of which said pair of nodes may be selectively connected.

7. A programmable logic gate substantially as hereinbefore described with reference to Figures 1, 2, 3, 5, 6,7 of the accompanying drawings.