FR2534091A1 - PROGRAMMABLE AND ELECTRICALLY DELETED ROCKER - Google Patents

Abstract

THE INVENTION CONCERNS LOGIC CIRCUITS. A SERIAL CIRCUIT CONNECTED BETWEEN V, V SUPPLY TERMINALS INCLUDES THE ADDITIONAL FIELD EFFECT TRANSISTOR CHANNELS 23, 24 WHICH HAVE THRESHOLD VOLTAGES THAT CAN BE ELECTRICALLY MODIFIED. THE TRANSISTORS, ONE FOR CONDUCTION AND THE OTHER FOR LOCKING, ARE PROGRAMMED BY APPLYING A PROGRAMMING VOLTAGE ON THEIR INTERCONNECTED GRIDS, TO FORM A PROGRAMMABLE TILT. SUCH A CHANGEOVER CAN BE USED WITH ASSOCIATED CIRCUITS TO SELECTIVELY CONTROL THE TRANSISTORS OF AN ADDITIONAL PAIR LOGIC INVERTER AMPLIFIER. APPLICATION TO THE PROCESSING OF DIGITAL OR ANALOGUE SIGNALS.

Description

The present invention relates to programmable electronic circuits and

electrically erasable,

  for handling digital or analog signals

  c. U UAO Patent No. 3,500,062 discloses

  EXCLUSIVE and NON-EXCLUSIVE-OR doors of the metal-type

  semiconductor oxide with complementary symmetry (or

  CMOS) In these circuits a first signal of

  logic among two is applied to a simple inversion

  a logical pair formed by a symmetrical pair of CMOS type, to obtain its logical complement. This first logical input signal is then used and its complement of

  selectively, either to validate a gateway

  mission to transmit-the second input signal

  logic without inversion to the logical output of the

  tesoit to validate a logic inverter consisting of a symmetrical pair of CMOS type, to apply to the logic output of the gate the inverted signal which is

  obtained in response to the second logic input signal.

  Field effect transistors have recently been developed which have threshold voltages, or V Te that can be electrically modified, or that can be programmed by applying voltages between the gate.

  and one of the other electrodes of the device, these tensions

  beyond those used as

  Then, a nonvolatile memory incorporated in these effect transistors

  field retains the programmed threshold voltage Demand -

  British Patent Publication No. 8,136,497 discloses the

  grammar threshold voltages of such devices for

  condition them so that they have characteristics

  corresponding to a very marked enrichment mode

  or a very marked mode of depletion, so that they

  and in open circuits or short-circuits for programmably interconnecting CMOS field effect transistors to form logic gates or logic gate networks. Threshold programming

  of these devices is accomplished by the application of

  programming stations through the terminals of

  used as normal logic inputs This uses two different signal regimes for different purposes, but with the application of signals by

  the same terminals, constitutes what is called

"reflex".

  The invention is implemented in an electrically programmable latch which comprises a first field effect transistor of a type whose threshold voltage can be programmed under the effect of the application.

  momentum of a programming voltage of se-

  selected between a gate electrode and one of the other electrodes of this transistor, for conditioning the first transistor in the enrichment mode or in the depletion mode, in accordance with the polarity of the transistor.

  programming voltage, so that the channel con-

  of the first transistor establishes a connection between a first source of supply voltage and a flip-flop output connection which is provided for

a charge.

  According to the invention, the flip-flop comprises a second transistor and a second source of supply voltage; the second transistor is of the type whose

  threshold voltage is programmable under the effect of the

  momentarily transmitting a programming voltage between the gate electrode and one of its other electrodes, so as to condition the second transistor in the enrichment mode or the depletion mode when the first transistor is respectively programmed to operate in depletion mode or enrichment mode; in order to produce on the output connection of the flip-flop

  a voltage almost equal to that of one of the first

  first and second sources, this voltage being selected

  in accordance with the polarity of the programming voltage

  which was last applied to the electrodes -de

  gate of the first and second transistors.

  Other features and advantages of the

  will be better understood when reading the description of

  following description of the modes of

  annexed drawings in which Figure I is a diagram, partly under

  synoptic form, of an electrically pro-

  grammable and erasable, consistent with an aspect of the invention

  tion; Figure 2 is a truth table for the Annis Gate

  Figures 3, 4 and S are diagrams of

  respective embodiments of an electrically programmable and erasable nonvolatile memory portion of the circuit of FIG. 1 which makes use of the invention

  Figure 6 is a modified version of the

  bake of Figure l allowing it to invert or not

  not reverse analog signals,

mable

  Figure 7 is a schematic diagram of variants of the

  bake of Figure 1 embodying other aspects of the invention; and Figures 8 to 13 are diagrams of additional respective embodiments of a portion of

  electrically programmable non-volatile memory and

  the circuit of Figure 1, which correspond to the

vention.

  In FIG. 1, an Annis gate 10 is provided to receive a logic variable A on its input terminal.

  11, from a source that is not explicitly referred to

  presented, and to receive another logic variable B and its complement B on its respective input terminals 12 and 13 The logic response C = Ae B appears on the terminal of

  exit 14 of the door 10, in accordance with the table of

  Figure 2, in which the letters H and L de-

  sign respectively high and low logic states.

  The symbol O designates the logical OR-EXCLUSIVE operation. Thus, C is the EXCLUSIVE-OR response to A and B. The point which differs from the prior art in the operation of the Annis gate is that logical variables B and B come from a circuit of

  flip-flop complemented, 20, which includes elements of

  electrically erasable and programmable dead memory (EEPROM), and in that logic conditions B and B are specified in accordance with previously applied programming signals on terminal 11.

  that the Annis 10 door can be programmed by the application

  cation of a programming potential located outside the

  within the normal range of logic signals, for

  then for C a value equal to A or A

  mites of a normal range of logic signals can be a relatively low voltage L which can be equal

  at the supply voltage VSS, and a relative voltage

  high, which may be equal to the power supply voltage

VDD.

  In the Annis gate 10, a n-channel enhancement field-effect transistor (TEC) 15, and a p-channel enrichment field-effect transistor 16 are connected together in the form of a pair of complementary transmission gate between terminals 11 and 14 When the latch 20 provides B = H and B = L, B being at

  the high state polarizes the gate of the n-channel TEC, 15,

  sound that he tends to drive for A <H, and B being in the state

  low polarizes the gate of the n-channel TEC, 16, so that it

  to drive for A> L The transmission gate connection

  TEC 15 and 16, between terminals 11 and 14, is conductive

  over the full range of normal logical levels which is bounded by H and L, so that we have C = A When flip-flop 20 provides B = L and B = H, B being low does not polarize the gate of the n-channel FET, 15, so that it is conducting at any logic level in the normal range, and B being high does not bias the gate of the p-channel FET, 16, to he is a driver

  at any logical level in the normal range.

  The transmission gate connection of TEC 15 and 16

  between terminals 14 and 11 is blocked.

  In the door of Annis 109 the grilles of a TEC

  enrichment and p-channel, 17, and an energetic

  and n channel, 18, are connected to the input terminal 11, and their drains are connected to the output terminal 14 When the sources of the p-channel TEC, 17 and n-channel TEC, 18, which receive respectively B and B, are respectively in the high state and in the low state, a

  logic inverter stage with complementary pair is valid

  between the input terminal 11 and the output terminal 14.

  So we have C = A (Usually, in the CMOS logical structure, the logical levels L and H have voltages that

  are closer to one another than the sum of the

  thresholds for p-channel enrichment and

  N channel that are used to realize the structure.

  This reduces the dissipation in that only TEC 17 can conduct in the presence of the condition A = L, and only the TEC 18 can lead in the presence of the condition A = H)

  On the contrary, when B = L and B = H, the inverse connection

  complementary pair of TECs 17 and 18 is

  invalidated because normal logical levels do not

  ploy of direct source-grid potential to none of the TECs. Starting from the configuration of FIG. 3, we will now consider the shapes 20, 20 ', 20 "that

  the complementary flip-flop circuit can be used to facilitate

  its programming via terminal 11.

  In FIGS. 3 and 4, the logic function B is complete

  in B by means of a logic inverter connection with

  In addition to the enhancement and p-channel FET 21, and the n-channel enrichment FET 22, the logical levels H and L can be identified at the respective positive and negative supply voltages VDD and

  VSSY in Figure 3 and the figures that follow.

  B from applied programming voltages

  terminal 11 involves the programming process.

electrically erasable

  An N-channel CTE 23 and a p-channel FET 24 of Figure 3 are of a type in which the voltage of

  TEC threshold can be programmed electrically by

  the potential between its gate and one of its electrodes a value significantly higher than the range

  corresponding to the normal excursion of logical levels.

  (A TEC with a programmable VT threshold voltage is

  shown schematically in the present application with an additional bar between the electrode portion of

  grid of the classical symbol of a TEC, and its parts cor-

  corresponding to the source, substrate and drain electrodes. This modified symbol is used independently of the

  that the programmable TEC is programmed by a

  programming gap between its gate and its drain electrode, between its gate and its source electrode, or between its gate and any other electrode or

  combination of electrodes) TEC 23 and TEC 24 are

  respectively shown in Figure 3 in the form of depletion and enrichment transistors, as they would be after a high voltage, significantly more positive than VDD in the case of injection devices by the grid, or significantly more negative than V Ss in the case of injection devices by the substrate, has been

  most recently applied as program voltage.

  terminal 11 The TEC 23 is conditioned by

  to be so deeply in the field of characteris-

  conduction ticks in depletion mode, that its channel is actually a short circuit to VDD, regardless of

  the value of A, between L = Vss and H = VDD inclusive, which is

  TEC 24 is conditioned to be so deep in the field of its enhancement mode conduction characteristics that its channel is non-conductive, regardless of the value of A, between L = Vss and H = VDD included, which is applied to its gate So we have B = VDD = H Therefore, the complementary-pair logic inverter connection of TEC 21 and 22 responds by giving B = Vss = L The Annis gate 10 is conditioned by B = H and B = L so as to be non-inverting, with the response

output C = A.

  However, when the programming voltage

  which was last applied by terminal 11 to the grills

  the TECs 23 and 24 was a high voltage,

  more negative than VSS, TECs 23 and 24 are

  are packaged in such a way as to have a strong

  enrichment and to have strongly the mode of

  So strongly that, for all the values of A between L = Vss and H = VDD included, applied to the gates of the TECs 23 and 24, the channel of the TEC 23 is non-conducting and the channel of the TEC 24 is a short-circuit to VSS So we have B = Vss = L

  and, therefore, B = VDD = H The Annis gate 10 is

  adjusted by B = L and B = H so as to be inverting, with

the output response C = A.

  The connection switches from 'TEC to common drains

  23 and 24, with a grid gate connection to receive

  see programming voltages and a connection of

  this to source as output connection, according to Figure 3, works with programmable TEC types

  by the application between the gate electrode and the electrode -

  drain or source electrodes (or optionally the substrate), with a voltage exceeding the normal sourcegrille voltages, such as, for example, gate-injection metal-oxide-semiconductor TECs (GIMOS structure). flip-flop, the flip-flop circuit complemented by FIG. 3, the flip-flop circuit complemented with FIG. 3 in combination with the complementary pair transmission gate, and the

  the flip-flop circuit complemented by FIG.

  pair with the complementary pair inverter (combined

  the sound of which one can also suppress the TEC 22), as well as the dual of this last circuit, are aspects

  of the invention are useful in themselves for realizing

  cooked other than the one shown.

  FIG. 4 shows a modified version 20 'of the complemented flip-flop circuit 20 of FIG. 3, in which the flip-flop configuration with FIGS.

  drains, 23 and 24, is replaced by a

  The TECs 25 and 26 are p-channel and n-channel, respectively, with respect to the type of conduction, and they have electrically modifiable threshold voltages which

  are programmed by applying a voltage of

  high grammage between their gate electrodes and their source electrodes (or possibly between their gate electrodes and their substrates) These transistors

  can be for example GIMOS TEC In the representa-

  tation, TEC 23 and 26 have been so strong-

  packaged for operation in the Ener-

  and for operation in depletion mode, respectively, as for VSS c A o VDD, the channel of the TEC 25

  is blocked and the TEC 26 channel is actually a short

  circuit to VSS This results from a programming voltage

  Noticeably more positive than VDD Due to a significantly more negative programming voltage than VSS, the TEC 26 can be programmed to be locked and the TEC 25 can be programmed to be in fact

  a short circuit to VDD The connection in circuit of

  25 and 26, the flip-flop circuit DC of FIG. 4, the complementary flip-flop circuit of FIG. 4 in combination with the transmission gate, FIG.

  complementary pair and the complementary flip-flop circuit

  FIG. 4 in combination with the complementary-money reverser, as well as modified versions of this circuit similar to those described in connection with the similar structure using the complemented flip-flop circuit of FIG. 3, in modified form, are aspects of the invention useful in themselves for the

  circuits other than the one

sented.

  Figure 5 shows a flip-flop circuit

  20 "compliant circuit breaker connection

  mable of common drain drains 23 and 24, and connec-

  programmable toggle of common source FETs 25

  and 26, both reacting to programming tensions.

  tion on terminal 11 by applying B and B to terminals 12 and 13, respectively, without requiring a logic inverter to control the position of Ensalpp Osat that the TECs 23,24, 25 and 26 silk d Ltpe to ijeot Dn by the grid, the last tenion of significantly more negatively applied programming than VSS has strongly polarized the p-channel TECs, 24 and 25, into operation in

  enrichment mode, to channel their channels into

  cooked open, in the presence of normal logical levels on

  their grids, and it strongly biased the TECs to

  Nal 23 and 26 in depletion mode operation, to short-circuit their channels for levels

  normal logic applied to their grids We can use

  a significantly higher programming voltage than VDD to open the channels of the TECs 23 and 26 and to short-circuit those of the TECs 24 and 25 for the application of normal logic levels to their gates. The flip-flop circuit complemented by FIG. 5

  and the combinations of this circuit with a transmission gate

  complementary pair mission and with a

  complementary pairs are aspects of the invention.

  useful in themselves for making circuits

very much as that represented.

  The programmable latches of FIGS. 3 and 4 are advantageous insofar as they do not consume

  no appreciable energy except during programming.

  These circuits can be modified to replace the TECs 23, 24, 25 and 26 by TECs with voltages of

  programmable threshold under the effect of a voltage of

  Grammation applied between their gate electrodes and their drain and source electrodes together To perform their programming, each of the VDD and VSS potentials is brought during programming to a value equal to a reference potential, and the connections of

  the flip-flop are forced to the reference potential

  Such forcing can be achieved by means of the selectively conducting channel of a TEC which is not

  the conductive state only during programming.

  It is possible to make adaptations of the circuit of FIG. 1 which make these terminals 11 and 14 be biased halfway between VSS and VDD, in the absence of application of a programming voltage.

  any or other input voltages at the terminal of

  This is advantageous for example when it is desired to use certain ternary logic configurations, or when it is desired to invert or not to invert selectively.

an analog signal.

  Figure 6 shows how one can achieve such an adaptation Resistors 27 and 28 of equal value

  average of B and B or VDD and VSS, for polari-

  Terminal 11 halfway between VSS and VDD.

  tance 29 ensures the centering of the idle voltage on the

  terminal 14 at mid "distance between VSS and VDD.

  FIG. 7 shows a programmable flip-flop 30 which is used to apply the programmed signal A to the input terminal A, 11, of the Annis gate

  enrichment and p-channel, 31, and an enrichment CET.

  and n channel, 32, are connected in a logic inverter

  complementary pair, to produce the signal F

  under the effect of the signal B, and these signals B and B are

  The programmable flip-flop 30 can receive programming voltages through its input connection 33 and the input signal B can be applied directly from the connection 33 to the terminal 12. ; or, as shown in FIG. 7, the programmable flip-flop 30 can receive programming voltages and the input signal U via a terminal 34, the signal B on the terminal 33 being inverted to apply the signal B at terminal 12 This inverter is performed in FIG. 7 using the connection

  in a complementary pair of logic inverter

  The p-channel FTE 37 and the n-channel FTE 38 in the programmable flip-flop 30 are preferably of the type whose VT threshold voltages are programmed. under the effect of programming voltages applied between their gate and source electrodes, when their

  channels are connected between VDD and V in the order

shown in Figure 7.

  Among the changes that can be made to

  the configuration of Figure 7, we can cite the following

  You can delete the N-channel 32 TEC if B is applied

  from the terminal 33 to the N-channel FET gate 16, in the transmission gate connection to the p-channel FET, instead of being provided by the terminal 13 The order of the

  connection of the external circuit to terminals 12 and 13 of the

  Annis te can be reversed; and this modification can be extended either to connect the terminals 13 and 14 and eliminate the TECs 35 and 36, or to eliminate the TEC 31 by

Z 534091

  connecting the TEC 15 grid to terminal 34 instead of the

connect to terminal 13.

  We can make variants of the circuit of the

  Figure 7 or any of its indi-

  above, in which there is an inversion in the programmable latch 30 of the p-channel TEC and programmable threshold voltage channel positions, 37, and

  N - channel FET with programmable threshold voltage, 38.

  TECs 37 and 38 must be of the type whose VT threshold voltages are programmable under the effect of voltages

  programming between the grid and the drain.

  There will be a corresponding inversion of the polarity of

  programming voltages to establish each of the conditions

  output of the programmable flip-flop.

  Structures can be

  Cereal the drain source electrodes of the TECs 37 and 38 during their programming, to allow each of them to be of a type programmed by the voltage applied between its gate and its source and drain electrodes, or between its grid and one of its source electrodes and

  drain that is not directly connected to a voltage

  supply voltage During programming, the voltages VDD and VSS are brought to a value equal to a reference voltage. We will now consider other modes of

  realization of the flip-flop circuit complemented by the invention

  8, 9, 10, 11, 12 and 13 In each of these figures, the transistors and

  other elements bear reference numbers which

  correspond to those of Figures 3, 4 and 5, with the aim of

  cilitate the explanation of the invention.

  In each of Figures 8-13, the logic function

  that B is complemented in B by a complementary pair logic inverter connection of the enriched and

  p-channel, -21, and enrichment and n-channel TEC, 22.

  The logical levels H and L can be identified at

  positive and negative supply voltages, respec-

* VDD and VSS, in Figure 2 and the figures

  follow Obtaining B from program voltages

  applied by the terminal. It involves the

  electrically erasable programming process.

  An N-channel GIMOS TEC 23 (MOS transistor with

  grid) and an N-channel MOS TEC, 24 (tran-

  substrate-injection MOS sistor) shown in FIG. 8 are of a type in which the threshold voltage of the TEC can be electrically programmed by

  the application between his-grid and another of these elec-

  trodes with a potential significantly greater than the normal excursion range of the logic levels The TEC 23 and TEC 24 are respectively represented in FIG. 8

  as depletion and modal mode transistors

  of enrichment, as they would be after a high voltage, significantly more positive than VDD was

  most recently applied as

  Gramming, through terminal 11 The TEC 23 is conditioned to be placed so deep into the field of depletion mode conduction characteristics that

  its channel is actually a short circuit to VDD, inde-

  of the value of A, between L = Vs $ and H = VDD included which is applied to its grid The TEC 24 is conditioned by

  to be so deeply in the field of its

  conduction characteristics in enrichment mode that its channel is blocked, regardless of the value of A, between L = Vss and H = VDD included which is applied to its grid

  therefore B = VDD = H Therefore, the inverter connection lo-

  complementary pair of TECs 21 and 22 responds in

  supplying B = V ss L The Annis-10 carrier is conditioned -

  by B = H and B = L so-to be non-inverted &, with the re-

output response C = A.

  However, when the programming voltage last applied by the terminal 11 to the gates of the TECs 23 and 24 has been a high voltage, significantly more negative than V, the TECs 23 and 24 are conditioned by

  to be strongly in enrichment mode respectively.

  and strongly in the depletion mode So strongly that, for all values of A between L = Vss and H = VDD included that are applied to the gates of the TECs 23 and 24, the channel of the TEC 23 is blocked and the channel of the TEC 24 is a short circuit to V 5 ss Under these conditions, B = Vss = L and therefore B = VDD = H The Annis gate 10

  * is conditioned by B = L and B = H so as to be inverted

  only, with the output response C = A.

  The floating gate structure of TEC GIMOS 23 is preferably made in such a way that the device

  react, for programming, to a voltage of

  grammage applied between its gate and drain electrodes, without terminal 12, to which its source is connected, must be forced to a reference voltage

  during programming The flow chart structure

  TEC SIMOS 24 is preferably

  that the device responds, for programming,

  to a programming voltage applied between his

  trodes of gate and source, or between its gate electrodes and desubstrat, without the terminal 12 to which its drain is connected must be forced to a reference voltage during programming When the TEC GIMOS

  23 is of a type whose source electrode must be

  a reference potential during programming, or when the SIMOS 24 TEC is of a type whose

  drain must be forced to a potential during the

  grammage, the forcing is simply carried out by the

  selectively conducting a TEC which is placed in the conductive state under the effect of a control signal

  applied to its gate electrode during programming.

  The programming voltage on terminal 11

-2534091

  can be applied to form this command signal.

  of, to a TEC having a suitable conductivity type and a sufficiently high effective threshold voltage (either by nature or with the aid of a potential shifter connected in its gate connection) The tilt connection of TEC 23 and 24, the flip-flop circuit

  complemented by Figure 8, the complete flip-flop circuit

  FIG. 8 in combination with the complementary pair transmission gate, and the complemented gate circuit of FIG. 8 in combination with FIG.

  the complementary pair inverter (combination of the-

  which one can also suppress the TEC 22) are

  aspects of the invention that are useful in themselves for realizing

  circuits other than the one shown.

  Fig. 9 shows a modified ion-counter 20 'of the complemented flip-flop circuit 20 of Fig. 8, in which the flip-flop configuration formed by the

  TEC GIMOS with common drain 23 and the SIMOS TEC with a common source

  mune 24, e-st replaced by a flip-flop configuration formed by a common drain SIMOS TEC 25 and a common source GIMOS TEC 26 The TEC 25 and 26 are both of the n-channel type, and the floating gate of the TEC is preferably made to react to a programming voltage between the gate and drain electrodes, while the floating gate of the TEC GIMOS

  26 is preferably made so as to react to a tendency to

  programming voltage applied between gate and source electrodes; this makes the forcing of the interconnection node between the TECs 25 and 26 unnecessary. The TECs 25 and 26 are represented in a state in which they have been so

  strongly conditioned respectively for the functioning

  In Enrichment mode and for depletion mode operation, for VA z VDD the TEC 25 channel is blocked and the TEC channel 26 is in fact a short circuit to VSS Thus, under the effect of a voltage 1 Ji is _netzmlb, 1roughs rain 'than 1 the DD. 2 m can be de fi ned, to others in one, and the TEC 25 can be withdrawn in such a way that it can be used as a standard. mezetli-ve-that 13 S, the TEZC 2 t 5 can Mtre ú> fe frv, one to be 'b 2 rqu' -and 2-e TEC

  can be prgraded to be in ú-is an e = -t-

  Either, it is the same as in the case of the TL-C 25 and Z 6, and the C-orriplem-ent of

  fdgure - 9, the first flip-flop circuit of the fi-

  station 9 are: The loss of tea-nzmissi Dn to

  pay: r B -and the vl, rc-iiit from baszm 2 eMPI- -

  2 e ffg gurn 9 in Vinverseur with pe-Te Sant of s-z p-ec-ts of 111: nycé-, ntïon in, e 1 îxm, m-zs pzur -des other circuits

hairy repressed.

  Fever 210 = be a zircuit of hes-cule eorplémentie 2 '0 l' -, which included the 1-en-lacuna

  p-rograrrkm Eble of TEC 23 and 24 and the con- nection of

  PD zulfe programmable TEC -2-e and 2 'B, both reacting

  te-n-s: ï-Dns -de p, o e He appl I -

  _r g-rammat-ïzm Bur: The terminal-respectfully 3 and 3 terminals 12 and 13, without requiring a reverser 2-ogïc-ue ai

j -to pair - completely re.

  such as I have applied to myself - which has been nd-more than V -, has strongly biased

  1-es TE-C '23 and 2-5 in the operating mode -dle-nrî-

  idhissement, ppow, put 1-eurz channels in open circuit p-cur Level = 1 ics normal on their grids', and

  a -o strongly ZEC 24 and 25 -in the fon-0-

  tnznne-mert -in -d-mode Z-ple-n-p-our short-circuit their

  Cana = pizur of the mivezux: L-o ,, gicic normal of their -grill-es.

  For fear of planning much more than to put in place: open the eves (TECs -2-4 and '25 and -for -c-or -rt-,

  TEC 2,3 (and 2-B, fear of no-one-at-il Zgl, which is 'n' 01-

  on their gates The complementary flip-flop circuit

  FIG. 10 and the combinations of this circuit with a complementary pair transmission gate and with a complementary pair logic inverter are aspects of the invention useful in themselves for realizing

  circuits other than the one shown.

  Like the latches of Figures 3, 4 and 5, the

  The programmable flip-flops of Figures 8, 9 and 10 are

  to the extent that they do not consume energy

  It is appreciated that, except during programming, each of the programmable flip-flops of FIGS. 8, 9 and 10 uses n-channel programmable threshold voltage transistors; and they have counterparts using programmable threshold voltage and p-channel transistors, as shown in FIGS. 11, 12 and 13 respectively. As in the case of the circuit of FIG. 1 using the flip-flops 20, 20 'and 20 " FIGS. 3, 4 and 5, the circuit of FIG. 1 using the flip-flop which is represented in each of FIGS. 8 to 13 can be

  designed to polarize its terminals 11 and 14 half way

  distance between VSS and VDD, by connecting the circuit of

  Figure 1 to the network shown in Figure 6.

  Some changes will now be described

  10 and 13 In the figure, it is possible to replace the two SIMOS-type N-channel TECs.

  GIMOS type p-channel FETs, or alternatively,

  place the two GIMOS N-channel TECs with TECs

  SIMOS type p-channel In FIG. 13, it is possible to replace

  place the two SIMOS p-type FETs with GIMOS-type N-channel FETs, or the two can be replaced

  GIMOS-type p-channel TEC with N-type N-channel FETs

SIMOS.

  In the following claims, one must

  that the class of metal-insulator-semiconductor transistors

  specified as being of the injection type by the

  grid encompasses other TECs with programmable threshold

  ble with electrically programmed and electrically erased conduction characteristics similar to that of a GIMOS TEC, such as Programmable Injection Types (PIMOS), and the specified class of metal-insulator-semiconductor transistors must be considered as a substrate injection type includes other programmable threshold voltage TECs having programmed and electrically erased conduction characteristics in a manner similar to that of the TECs.

SIMOS.

  Of course various modifications may be made by those skilled in the art to the device and method described and shown, without departing from the scope of the invention. ICE 116 ATIl 6 E $ 1 3 electrically controllable ascultor (20 ', 20 "), comprising: a first transistor (23) of a type whose threshold voltage is programmable under the effect of a momentary application of a voltage of pro - polarity grammar selected between an electrode

  gate and one of its other electrodes, for condi-

  this first transistor so that it works

  in enrichment mode or in depletion mode

  tion of the polarity of the programming voltage which

  is applied to the gate electrode; the channel of con-

  duction of this first transistor being connected between a first supply voltage source (DDBD) and

  an output connection of the flip-flop (B) for a

  ge; characterized in that the load consists of a

  conduction circuit of a second connected transistor (24)

  between the output connection of the flip-flop and a sec-

  of a supply voltage source (VS), this second transistor being of a type whose threshold voltage is prograomiable under the effect of the momentary application of said programming voltage between an electrode of

  grid and one of its electrodes {source),

  to condition the second transistor so that it

  in the depletion mode when the first transistor is programmed to operate in enrichment mode, and to operate in enrichment mode when the first transistor is programmed to operate in operation.

  mode of depletion; in order to produce on the conne-

  output of the flip-flop a voltage substantially equal to one of the first and second supply voltages, the

  voltage produced being selected in accordance with

  of the programming voltage that was last applied to the gate electrodes of the first and second transistors. 2 electrically programmable switch according to claim 1, characterized in that it further comprises a logic inverter which comprises third and fourth field effect transistors (21, 21 ') having

  opposite conductivity types, including grill electrodes,

  are connected to the output connection of the flip-flop and whose conduction channels are connected in series

  between the first and second sources of power supply

  to produce on an inverse output connection

  (B) formed at the junction of the channels connected in se-

  the complement of the voltage present on the conne-

output of the flip-flop.

  3 Electrically programmable scale (20) sec-

  claim 2, combined with a transmission gate

  sion in order to selectively connect a first

  node (11) and a second node (14) which form a

  circuit section (C); characterized in that gate electrodes of a fifth and a sixth field effect transistor (15, 16) of opposite conductivity types,

  of the transmission gate, are connected to conne-

  respective xions from the output connection of the base

  (B) e-t the output connection of the inverter (B) and

  conduction channels of the fifth and sixth transistors

  tors are connected in parallel between the first and second

cond knots.

  An electrically programmable scale according to claim 3, further combined with an inverting amplifier, characterized in that conduction channels

  connected in series of seventh and eighth

  field effect tor (17, 18), of opposite conductivity types

  of the amplifier inverter are connected at a connection point to each other at the circuit output connection (C) and are connected between the

  output of the flip-flop and the output connection of the invert-

  seur (B); and gate electrodes of the seventh and eighth

  tth field effect transistors are connected to each other

at the first node.

  An electrically programmable scale according to claim 2, combined with an amplifier inverter, characterized in that conduction channels connected in series with a fifth and a sixth field effect transistor (17, 18) of opposite conductivity types of the amplifier inverter establish a circuit output connection (C) at a connection point

  between them, and these channels are connected between the connec-

  output of the flip-flop (B) and the output connection

  part of the inverter (B); and grid electrodes of

  fifth and sixth transistors are connected to each other

and at a first node.

  6 Electrically programmable scale according to

  any of claims 1 to 5, characterized

  in that the programming voltage level at which

  the first and second transistors react is superior

  the voltage level provided by the first and second sources of supply voltage; so that the thresholds of the first and second transistors remain unchanged in the presence on the input connection of a logic signal whose voltage is less than or equal to the difference between the voltages of the first and second transistors.

  second sources of supply voltage.

  An electrically programmable scale according to claim 1, incorporated in a circuitycharacterized in that it further comprises: an output connection

  circuit (14); and an additional field effect transistor

  (15, 16 or 18) of which one of the electrodes of

  this, gate and drain is connected both to a circuit input connection (A) and to the gate electrodes of the first and second transistors, and the gate electrode of this additional transistor, if not not otherwise connected, or another of its electrodes

  source and drain, is connected to the output connection

  of the flip-flop, while the remaining electrode

  the source and drain electrodes of the

  Complementary is connected to a circuit output connection (C); so that the additional field effect transistor responds to a logic level signal applied to the input connection by producing on the

  circuit output connection a signal that is func-

  of the logic level signal and the polarity of

  the programming voltage applied in the last

  deny to the circuit input connection.

  8 Electrically programmable scale according to

  claim 7, characterized in that the electro-

  source and drain of the additional transistor (15 or 16) are connected between the circuit input connection and the circuit output connection, and the gate electrode of the further transistor is

  connected to the output connection of the flip-flop.

  Electrically programmable scale according to claim 7, characterized in that one of the

  source and drain electrodes of the

  element (18) is connected to the output connection of the flip-flop, the other electrode

  source and drain of the additional transistor is con-

  connected to the output connection of the circuit, and the gate electrode of the additional transistor is connected to the

circuit input connection.