JPS61114556A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the reduction of resistance in a conductive layer and the reduction of an interlayer insulation film by using a mask covering the field around the exposed gate electrode of a source drain forming region and the exposed wiring of the gate electrode. CONSTITUTION:A field insulation film 5 and a thin insulation film 3 are formed on a semiconductor substrate 1. The gate electrode 41 on the insulation film 3 and the wiring 42 of the gate electrode are formed to a required pattern shape by a conductive layer. A mask layer 6 made of a resist material is formed on the surface of the field insulation film 5 leaving only source drain forming regions 11, 12, the gate electrode and the wiring 42 of the gate electrode. In this state, impurity for forming source drain is implanted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a single conductivity type MOS (MOS) transistor or CMOS transistor.

BACKGROUND OF THE INVENTION Generally, MOS transistors are manufactured using gate electrodes and gate electrodes. -) It is desired to lower the resistance of the conductive layer such as polycrystalline silicon that constitutes the electrode wiring part, and as a means to achieve this, conventional methods include impurity gas diffusion and impurity ions for source/drain formation. Methods such as implantation are being considered.

Among these methods, the former method involves forming a field insulating film and a thin gate insulating film on a semiconductor substrate, and then coating the polycrystalline silicon layer formed on these insulating films with a material such as phosphorus for the purpose of lowering the resistance. Impurities are introduced by gas diffusion. However, in this case, if the amount of impurities is too large, the etching process will be carried out in the next etching process (a process in which unnecessary parts of the polycrystalline silicon layer are removed by etching, leaving the gate electrode part and gate electrode wiring part). Since the no-turn shape of the polycrystalline silicon layer after etching is damaged (it is not etched cleanly), there is a limit to the amount of impurities that can be introduced, and this method alone cannot sufficiently achieve the above purpose of lowering the resistance. I can't.

Therefore, in order to supplement the resistance reduction means by the impurity gas diffusion, in the source/drain formation step that is performed after the impurity f gas diffusion step and after the formation of a polycrystalline silicon layer. Impurity ions for forming sources and drains are also implanted into the polycrystalline silicon layer.

FIG. 4 is a plan view showing, as dotted line regions, regions into which impurity ions for forming the source and drain are implanted in the prior art. In the figure, FIG. 4 (IL) shows the case of a single conductivity type (N channel or P channel) MOS transistor, in short, the source/drain forming regions 11 and 12 and the low resistance The impurity ions are implanted into the entire surface of the polycrystalline silicon layer that is desired to be formed, including the r-) electrode portion 41 adjacent to the source/drain forming region and the r-upper electrode wiring portion 42 leading to the electrode portion. Yes, the source/drain formation regions 11 and 12 are formed by such a simple process.
As the drain is formed? -) The resistance of the polycrystalline silicon layer forming the electrode portion and the gate electrode wiring portion is reduced. Note that as the impurity ions to be implanted, for example, in the case of an N-channel transistor, phosphorus or arsenic ions are used.

However, in such conventional technology, since the entire surface including the source/drain formation region and the polycrystalline silicon layer is used as the ion implantation region as described above, the area other than the source/drain formation region and the polycrystalline silicon layer, i.e. The ions are also implanted into the surface portion of the field insulating film 50 that separates adjacent elements.

However, when ions invade the surface of the field insulating film in this way, the film quality of the insulating film changes and it becomes easily scratched (not easily etched), and the next layer, such as the polycrystalline silicon layer and the aluminum layer. In the pretreatment process performed before starting the process of forming an interlayer insulating film (usually made of PSG) for insulating the wiring, the surface of the insulating film into which the ions have penetrated is scratched, resulting in the insulation between the eyebrows. The number of eyes decreases. As a result, the distance between the aluminum wiring formed on the glabellar insulating film and the semiconductor substrate is shortened, and the aluminum wiring capacitance increases accordingly.

Moreover, in both FIGS. 4(b) and 4(C), -
The source of a conductive type device (for example, an N-channel device)
FIG. 3 is a plan view showing a region where impurity ions for forming a drain are implanted (the implantation region is shown as a sandy hatched region).

In other words, in the case of FIG. 4(b), when implanting impurity ions for forming the source and drain of a negative conductivity type element,
source/drain forming regions 112, 122 of an element (for example, a P-channel element) of a conductivity type opposite to the - conductivity type;
If the y-to electrode part 412 and substrate contact area of the element exist, the entire surface excluding them (i.e.,
- Source/drain formation region 111°1 of conductive type element
21. e-) Electrode portion 411 and gate electrode of the device.

The polar wire portion 421 is of an element of a conductivity type opposite to the − conductivity type.
-) The electrode wiring portion 422, the base contact region (not shown) of the element of the opposite conductivity type, and the field insulating film 5) are used as the ion implantation region.

On the other hand, in the case of FIG. 4(c), the source of the − conductivity type element
When implanting impurity ions for drain formation, the -
Source/drain formation regions 111, 12 of conductive type elements
1. Only the gate electrode portion 411 of the device and the base contact region (not shown) of the device of the opposite conductivity type are used as ion implantation regions. After implanting ions for forming the source/drain of the device of the opposite conductivity type, either the method shown in FIG. 4(b) or (c) above is applied. The implant area has been selected.

However, in the case of FIG. 4(b) above, since the ions are also implanted into the field insulating film 5, it is clear that there is a problem similar to the case of the single conductivity type shown in FIG. 4(a). It is. On the other hand, in the case of Fig. 4(c), the field absolute R
Since the ions are not implanted into the film, the above-mentioned problem does not occur, but since the ions are not implanted into the gate electrode wiring portions 421 and 422, there is a problem that the purpose of lowering the resistance of that portion cannot be sufficiently achieved. there were.

Problems to be Solved by the Invention The present invention has been made in view of the problems of each of the above-mentioned conventional techniques. This also achieves the reduction in resistance of the conductive layer made of polycrystalline silicon or the like.

Means for Solving the Problems According to the present invention, a mask is used which exposes at least the source/drain forming region, the gate electrode part, and the gate electrode wiring part, and which covers the field part around them,
A method of manufacturing a semiconductor device is provided in which impurities for forming a source and drain are implanted through the mask opening.

Operation According to the present invention, when impurities for forming source/drain are implanted, the impurities are also implanted into the r-to electrode portion and the r-to electrode wiring portion, and these impurities are implanted into the gate electrode portion and the r-to electrode wiring portion.
- The resistance of the polycrystalline silicon layer constituting the electrode wiring part is lowered, and the source/drain forming region, r-)
Since the remaining portion excluding the electrode portion and the gate electrode wiring portion, that is, the surface portion of the field insulating film, is covered with a mask during the impurity implantation, the impurity ions do not enter the surface portion of the insulating film. Therefore, it is possible to prevent the aluminum wiring capacitance from increasing as described above due to the surface portion of the insulating film being scratched in subsequent processing steps.

Embodiment FIG. 3 is a plan view showing the region where the impurity ions for forming the source/drain are implanted in the present invention (the implantation region is shown by a sandy hatched region).
3(a) shows the case of a single conductivity type MO8) transistor, and FIG. 3(b) shows the case of a MO8) transistor.

In other words, in the case of the single conductivity type shown in FIG. It is limited to the r-to electrode wiring 42.

On the other hand, in the case of the 0MO8) transistor shown in FIG. The regions into which impurity ions for forming the source and drain of an element (for example, an N-channel element) are implanted are the source and drain forming regions 111 and 121 of the - conductivity type element, the gate electrode portion 411 of the element, and the f −
421, and the conductivity type of the element opposite to the negative conductivity type. -) [limited to the marking line portion 422 and, if necessary, the substrate contact region (not shown) of the element of the opposite conductivity type. After implanting impurity ions for forming the source and drain of the element of the - conductivity type, impurity ions for forming the source and drain of the element of the opposite conductivity type are implanted. Source/drain forming regions 112° 122 of the type element, gate electrode portion 412 of the element
and a substrate contact region (not shown) of a device of one conductivity type K implant.

In the present invention, in order to limit the ion implantation region to each of the above-mentioned regions, a mask is used that has holes formed above the ion implantation region and covers the surrounding field portions during ion implantation.

Hereinafter, a specific example of a method for manufacturing a semiconductor device according to the present invention will be described in which the impurity ion implantation region for source/drain formation is limited to the above-mentioned range.

FIG. 1 shows a state in which a mask layer is formed to limit the implantation region υ when impurity ions for forming the source and drain are implanted during the manufacture of a semiconductor device according to the present invention. It is shown in a perspective view.

That is, a well-known field insulating film 5 and a thin insulating film 3 are formed on a semiconductor substrate 1, and an r-) electrode part 41 on the insulating film 3 and a gate electrode wiring part 42 connected to the gate electrode part 41 are formed in multiple layers. After forming a conductive layer made of crystalline silicon or the like into a predetermined turn shape, only the source/drain forming regions 11 and 12, the gate electrode portion 41, and the #gate electrode wiring portion 42 are left, and the other portions, i.e. A mask layer 6 made of a resist material is formed on the surface of the field insulating film 5, and in this state, impurity ions for forming the source/drain are implanted.

In this way, the source/drain regions 2 of a predetermined conductivity type are
1.22 is formed, and the ions are also implanted into the polycrystalline silicon layer constituting the gate electrode portion 41 and the gate electrode wiring portion 42, thereby reducing the resistance of these portions. On the other hand, the surface portion of the field insulating film 5 is covered with a mask layer 6.
Since the field insulating film 5 is covered, the ions will not enter the field insulating film 5, and therefore there is no fear that the insulating film 5 will be dislodged in subsequent processing steps.

Note that a normal resist material is used as the mask layer.

In addition, in FIG. 1, the thin insulating film 3 is
Although the ion implantation is shown to be performed with the ions left only directly under the source/drain forming regions 11.
Ion implantation can also be performed with the top of the semiconductor device 12 covered with the insulating film 3 or an insulating film grown separately.

After implanting ions of a predetermined conductivity type only into the source/drain forming region, the gate electrode portion, and the electrode wiring portion as described above, the mask 6 is removed, and then the normal process is followed. As shown in Figure 2, a thin oxide film 7,
An interlayer insulating film 8 made of PSG, an electrode contact window (not shown), and an aluminum wiring 9 are formed.

Note that when manufacturing an 0MO8 transistor according to the present invention, first, as shown in FIG. - Source/drain formation regions 111, 121 . of conductive type elements. Gate electrode section 411e of the element
-) Using a mask in which holes are formed only in the electrode wiring portion 421, the gate electrode wiring 422 of the element of a conductivity type opposite to the conductivity type, and the base contact region (not shown) of the element of the opposite conductivity type. to limit the ion implantation range to the above-mentioned range, then remove the mask, and then remove the source/drain forming regions 112 and 122 of the device of the opposite conductivity type, the gate electrode portion 412 of the device, and the device of one conductivity type. Impurity ions for forming the source and drain of the element of the opposite conductivity type may be implanted using a second mask in which only the substrate contact region (not shown) is opened. Thereafter, the second mask is also removed, and thereafter, a thin oxide film 7, a glabellar insulating film 8, an electrode contact window (not shown), an aluminum wiring 9, etc. are formed according to the usual process.

The present invention is not limited to reducing the resistance of all of the gate electrode wiring portions, but may be used to lower the resistance of some required portions of the gate electrode wiring portions.

Effects of the Invention As is clear from the above, the manufacturing method of the present invention can reduce the resistance of the conductive layer made of polycrystalline silicon or the like that constitutes the gate electrode part and the r-) electrode wiring part, and improves the interlayer insulation. It is also possible to prevent thinning of the film, that is, to reduce the aluminum wiring capacitance.

[Brief explanation of drawings]

FIG. 1 is a perspective view for explaining intermediate steps in manufacturing a semiconductor device according to the present invention, and FIG. 2 is a configuration of a semiconductor device manufactured through the manufacturing process shown in FIG. 1. FIGS. 3(A) and 3(b) are a cross-sectional view for explaining the present invention, and FIG. , (b) and (e) are plan views each illustrating a region into which impurity ions for forming a source/drain are implanted in the prior art. (Explanation of symbols) 1... Semiconductor substrate, 11.12... Source/drain formation region, 21.22... Source and drain,
3... Thin absolute R film, 41... r-) electrode part, 42...
... r-to electrode wiring section, 5... field insulating film, 6
...Mask layer, 7... Thin oxide film, 8... Interlayer insulating film, 9... Aluminum wiring, 111, 121...
- Source/drain formation region of conductive type element, 411
... Date electrode portion of the element, 421... f of the element
- electrode wiring part, 112, 122... source/drain formation region of the element of opposite conductivity type, 412... e of the element
-) Electrode part, 422...of the element? -) Electrode wiring section. Figure 1] Figure 2

Claims (1)

[Claims] 1. Using a mask that exposes at least the source/drain forming region, the gate electrode section, and the gate electrode wiring section and covering the field section around them, the source is exposed through the opening in the mask. - A method for manufacturing a semiconductor device characterized by implanting impurities for forming a drain. 2. At least the source/drain forming region, gate electrode portion, and gate electrode wiring portion of the element of one conductivity type, as well as the gate electrode wiring portion of the element of the opposite conductivity type are exposed, and the field portion and the surrounding field portion thereof are exposed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a mask is used to cover the gate electrode portion of the opposite conductivity type element and the source/drain formation region.