JPS61113245A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61113245A JPS61113245A JP23558584A JP23558584A JPS61113245A JP S61113245 A JPS61113245 A JP S61113245A JP 23558584 A JP23558584 A JP 23558584A JP 23558584 A JP23558584 A JP 23558584A JP S61113245 A JPS61113245 A JP S61113245A
- Authority
- JP
- Japan
- Prior art keywords
- wax
- layer
- semiconductor
- substrate
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
Description
本発明は、同一基板上に複数の半導体片がろう付けされ
る半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor pieces are brazed onto the same substrate.
同一基板上に複数の半導体片を固着する方法としては接
着材を用いて接着することも考えられるが、半導体片の
温度上昇が見込まれる電力用半導体装置においては信頼
性の点で問題がある。一方、半導体片の面に金属被覆を
施し、はんだなどのろうを用いてろう付けする方法は、
基板を加熱しておく必要があり、最初にろう付けした半
導体片は他の半導体片のろう付は工程の間ろうが溶融状
態で放置されているため、半導体片のろう付は面の金属
の褒賞あるいはろうとの合金化の進行により固着強度の
劣化を招くことがある。One possible method for fixing a plurality of semiconductor pieces on the same substrate is to use an adhesive, but this poses a problem in terms of reliability in power semiconductor devices where the temperature of the semiconductor pieces is expected to rise. On the other hand, the method of applying metal coating to the surface of a semiconductor piece and brazing it with solder or other wax is as follows.
It is necessary to heat the board, and when brazing the first semiconductor piece to another semiconductor piece, the solder is left in a molten state during the process, so when brazing a semiconductor piece, the metal on the surface Proceeding of alloying with the reward or wax may lead to deterioration of the bonding strength.
本発明は、上述の欠点を除去し、複数の半導体片を基板
上に逐次ろう付けする際、先にろう付けされた半導体片
の表面の金属被覆の炭室あるいはろう付は強度の低下を
防止できる半導体装置の製造方法を提供することを目的
とする。The present invention eliminates the above-mentioned drawbacks, and when a plurality of semiconductor pieces are sequentially brazed onto a substrate, the charcoal chamber or brazing of the metal coating on the surface of the semiconductor piece that has been brazed first prevents the strength from decreasing. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can be manufactured using the following methods.
本発明によれば、基板上に複数の個々に融点の異なるろ
う層の領域を形成し、基板温度を高めた後低下させる過
程において、融点の高い方のろう層領域から順次半導体
片を金属被覆を設けた表面によってろう付けすることに
より、先にろう付けされた半導体片の高融点のろうを順
次凝固させながら低い融点のろうによって後の半導体片
のろう付けを行うことにより上記の目的が達成される。According to the present invention, a plurality of solder layer regions each having a different melting point are formed on a substrate, and in the process of increasing and then lowering the substrate temperature, semiconductor pieces are sequentially coated with metal starting from the solder layer region having a higher melting point. The above objective is achieved by sequentially solidifying the high melting point solder of the semiconductor piece that has been brazed first, while brazing the subsequent semiconductor piece with a low melting point solder. be done.
以下本発明を二つの半導体片に対する実施例を引用して
説明する。第1図Ta+に断面図、第2図に平面図で示
すセラミック基板lの二つの領域に金属ペーストの焼付
けによって金属被覆を施し、その上に予備ろう層2.3
を設ける。予備ろう層2のろうは予備ろう層3のろう、
例えば5a63%のはんだより高融点のろう、例えばS
口1o%のはんだを選ぶ、この基板1を加熱したヒート
ブロック4の上に載せ、両予備ろう層2.3が溶融した
のち第一の半導体片5をろう層2の上に置き、ろう付け
をする。ついでヒートブロック4の温度を第3図に示す
ように次第に下げる。温度Aははんだ層2のはんだの融
点、温度Bははんだ層3のはんだの融点を示す、ヒート
ブロック4の温度がAより低くなるとはんだ層2がil
[ffiする。ここで第二の半導体片6を溶融している
予備はんだ層3の上に置きろう付けする。この際はんだ
層2はすでに凝固しているため長く溶融状態に放置され
ることはなく、半導体片のろう付は面に形成されたTI
/Ill/^U蒸着膜あるいはNl/Auめうきのよう
な金属被覆の半導体あるいははんだとの合金化の進行に
よるろう付は強度の低下などの悪影響を防止することが
できる。
以上の実施例では半導体片が2個であったが、より多数
の半導体片を同一基板上に固着する場合もそれに応じて
多種類の融点を有するろうを用いることにより同様に本
発明を実施できる。またセラミック基板に限定されず金
属基板の場合も実施できろ。
【発明の効果]
本発明は、複数の異なる融点のろう層を同一基板上に形
成し、次第に低下する基板温度に応じて融点の高いろう
層の上から順に半導体片をろう付けすることにより、す
でにろう付けされた半導体片が長くろう溶融の状態で放
置されず、ろう溶融状態の持続に伴う悪影響を防止する
ことができる。
この方法はダイボンダなどを用いた半導体装着の自動化
の際にも適用でき、得られる効果は極めて大きい。The present invention will be described below with reference to embodiments for two semiconductor pieces. A metal coating is applied to two areas of the ceramic substrate l shown in a cross-sectional view in FIG. 1 Ta+ and a plan view in FIG. 2 by baking a metal paste, and a preliminary brazing layer 2.
will be established. The wax in the preliminary wax layer 2 is the wax in the preliminary wax layer 3,
For example, solder with a higher melting point than 5a63% solder, such as S
Select 1% solder. Place this substrate 1 on a heated heat block 4, and after both preliminary solder layers 2 and 3 have melted, place the first semiconductor piece 5 on the solder layer 2 and braze. do. Then, the temperature of the heat block 4 is gradually lowered as shown in FIG. Temperature A indicates the melting point of the solder in the solder layer 2, and temperature B indicates the melting point of the solder in the solder layer 3. When the temperature of the heat block 4 is lower than A, the solder layer 2 becomes il.
[ffi. Here, the second semiconductor piece 6 is placed on the melted preliminary solder layer 3 and brazed. At this time, since the solder layer 2 has already solidified, it is not left in a molten state for a long time, and the solder layer 2 is not left in a molten state for a long time.
Brazing by progressing alloying of a metal coating such as /Ill/^U vapor deposited film or Nl/Au plating with a semiconductor or solder can prevent adverse effects such as a decrease in strength. In the above embodiment, there were two semiconductor pieces, but the present invention can be implemented in the same way when a larger number of semiconductor pieces are fixed on the same substrate by using solders having various melting points accordingly. . Also, it should be possible to implement it not only for ceramic substrates but also for metal substrates. Effects of the Invention The present invention forms a plurality of solder layers with different melting points on the same substrate, and brazes semiconductor pieces in order from the top of the solder layer with a higher melting point as the substrate temperature gradually decreases. Semiconductor pieces that have already been brazed are not left in a molten state for a long period of time, and adverse effects caused by the continuation of a molten state can be prevented. This method can also be applied to the automation of semiconductor mounting using a die bonder, etc., and the effects obtained are extremely large.
第1図は本発明の一実施例の製造工程を順次示す断面図
、第2図は第1図(舗に対応する平面図、第3図は第1
図のヒートブロックの温度経過線図である。
l:セラミック基板、2:高融点ろう層、3+低融点ろ
う層、4Iヒートブロック+5.6+半導体片。
第1図
時間 第3図Fig. 1 is a cross-sectional view showing the manufacturing process of an embodiment of the present invention, Fig. 2 is a plan view corresponding to Fig. 1 (Fig.
It is a temperature course diagram of the heat block of a figure. 1: ceramic substrate, 2: high melting point solder layer, 3+low melting point solder layer, 4I heat block +5.6+ semiconductor piece. Figure 1 Time Figure 3
Claims (1)
、基板上に複数の個々に融点の異なるろう層の領域を形
成し、基板温度を高めた後低下させる過程において融点
の高い方のろう層領域から順次半導体片を金属被覆を設
けた表面によってろう付けすることを特徴とする半導体
装置の製造方法。1) When brazing multiple semiconductor pieces onto the same substrate, multiple solder layers with different melting points are formed on the substrate, and in the process of increasing and then lowering the substrate temperature, the wax with the higher melting point is used. 1. A method of manufacturing a semiconductor device, characterized in that semiconductor pieces are sequentially brazed from a layer region to surfaces provided with a metal coating.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23558584A JPS61113245A (en) | 1984-11-08 | 1984-11-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23558584A JPS61113245A (en) | 1984-11-08 | 1984-11-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61113245A true JPS61113245A (en) | 1986-05-31 |
Family
ID=16988175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23558584A Pending JPS61113245A (en) | 1984-11-08 | 1984-11-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61113245A (en) |
-
1984
- 1984-11-08 JP JP23558584A patent/JPS61113245A/en active Pending
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