JPS61112283A - Graphic paint-out circuit - Google Patents

Abstract

PURPOSE:To paint out the inside of a drawn graphic frame at a high speed by using a hardware logic that can recognize a lateral contact of a circle or an apex of a polygon drawn on a graphic memory. CONSTITUTION:When a graphic is drawn to a drawing graphic memory 6 via a graphic control part 1, both X and Y registers 8 and 11 are initialized through a timing control part 2. These initialization values are preset to X and Y coordinate counters 9 and 12 as well as a graphic memory address counter 4 through a switch gate 3. Then 1 0 change detecting counters 21 and 22 count the 1 0 changes for each dot line through the memory 6. The address values of those changing points are stored to FIFO memories 19 and 20 respectively. In such a way, a control circuit of an inter-2-dot paint-out system is obtained to attain the paint-out of a graphic at a high speed with no crossing.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical field to which the invention pertains The present invention relates to a graphic room fill logic circuit in a graphic processing control device, and particularly to a circuit for filling non-intersecting polygons in a two-point fill control system for figures. It is.

2. Description of the Related Art Conventionally, in this type of graphic processing device, when filling out the inside of a drawn figure shown in FIG. Determine the coordinates of each dot, and from that vertex to 1 on the opposite side.
K has been realized either by drawing a straight line for each dot and filling it in, or by using a program to find only the coordinates of the vertices in the time order of polygon filling, and notifying the point-to-point filling control section.

However, these methods have disadvantages in that the program is complicated, the number of program steps increases, and the processing performance is slow.

Purpose of the Invention The present invention has been made in view of the above-mentioned conventional circumstances.
Therefore, an object of the present invention is to configure hardware logic that can recognize horizontal tangent points of circles or vertices of polygons drawn on a drawing memory, to eliminate the above-mentioned drawbacks, and to provide high-speed drawing and nine The purpose of the present invention is to present a new figure filling circuit that can fill in the inside of a figure frame.

Structure of the Invention In order to achieve the above object, the graphic amount crushing circuit according to the present invention detects the transition from 1 to O in every dot line in order to recognize the vertices of polygons and the horizontal contact points of circles. It has a detection circuit, a counter that stores the number of detections, and a FIFO memory that stores the address value of the drawing memory, and also includes a circuit that detects the first and last dot lines where "1" exists in the drawing memory space. Thus, it is possible to recognize vertices and contact points, and the circle or polygon drawn in the drawing memory can be filled in at high speed.

Embodiment of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. The drawing control unit 1 shown in FIG. 2 stores the polygon α (A, B, G, D, E) shown in FIG. 1 in the drawing memory 6.

A case will be described in which a figure F, G) is drawn and this figure α is filled in.

When the drawing control unit 11C finishes drawing the drawing memo 1J6ic figure α, the timing control unit 2 sets the X coordinate register 8. The Y coordinate register 1 is initialized, and the value is preset in the X coordinate counter 9 and the Y coordinate counter 2, and is also set in the drawing memory address counter 4 through the switching gate 3, and the value is set in the drawing memory 6 for each dot line. The contents are read out one dot at a time, passed through the 1→0 detection control circuit 7, and then passed through the switching gate 5 again to the drawing memo 17.
6 is written. The content read from drawing memory 6 is
In the case of 1'', the data subsequently read from the drawing memory 6 becomes O'', and until 1m is read again, @1'' is written to the drawing memory 6 by the 1→0 detection control circuit 71C. Every time 8.1 is written to the drawing memo 176, the X coordinate color/reference 9 and the drawing memory address counter 4 are incremented. X by the comparison control circuit 10
The value of the coordinate counter 9 is constantly checked, and when the final value of the X coordinate is reached, the timing control section 2 is notified, the X coordinate counter 9 is preset again, and the Y coordinate counter 12 is incremented. Furthermore, from the 1→O detection counter 4 and the FIFO memory 19, the 1→0 detection power and/or ρ, FI
Switched to FO memory addition.

The comparison arithmetic control circuit section n uses this 1→0 detection counter 21,
22, and when the two counter values are different, or when one dot line processing is completed due to the difference, correction is made to the contents of the drawing memory 6 for that dot line. When a 1→0 state is detected by the 1→0 detection control circuit 7, the value of the drawing memory address counter 4 is stored in the FO memory 19 or FIFO memory 20, and the 1→0 detection counter 21 or n is incremented. do.

Next, the drawing memo by the comparison/arithmetic control circuit section]7
I will explain when adding c correction. This will be explained with reference to FIG. 1 (3).

Let ga and lb be dot lines passing through each vertex of figure α.

lc, le, lfd, the dot line around one dot is 'a-1+ 1a+, *b-4m'
b+11 IC-1+ 'c+1 +16-1* l
This will be explained as e+1+'fd-1+'fd+4. first,! At Knee 1 7F-in, the value of 1->O detection counter 21 is 0, and at M-line, the value of 1->O detection counter n is 11''. Since the difference is @1'', the comparison calculation control unit n reads the drawing memory address value of the next dot of xa from the FIFO memory IJ 20, sets it in the drawing memory address counter 4, and sets it in the drawing memory address counter 4. 7 is given the write data to the drawing memory 6 as K"0', and rewritten from the address of Xa+1 of the la dot line. In this case, 1→O detection counter 21,
22 and F memory 19.20 are not changed. Next, read the l dot line and read out a+1, and when 1" is detected at X1a+1, the first order "1" (
Until X2a+1) is read out, the write data content from the 1→0 detection circuit 7 to the drawing memory 6 is always set to "1"K. Therefore, %'a-H dot line X1a+1
Between "2a+1", "1n" is written in the drawing memo 1J61c, and "0" is written after x2a+. 'When the processing of the a+1 dot line is completed, the 1→0 detection counter 21
The value of is 2, which is an even number, and the value of the 1→O detection counter n of the la dot line is 1, so the difference is 1, so VC1
'a+1 dot line processing is normal and comparison calculation control circuit n
recognizes. The next 'a+2 dot line is also processed in the same way as the 'a+1 dot line, and as a result, the 1→0 detection counter n value is 2, an even number, and the difference from the 'a+1 dot line is O, which is also considered normal. Process and move to C.

The 1c-1 dot line is also filled with 11" between xIC-1" and 2C-1 using the same process as the 'a+1 dot line.

After X2o-4, it becomes O. The treatment result is lc-.

The value of the 1→O detection counter 21 on the dot line is 2, which is F.
IFO, + -v= IJ 191C (Xl.-i
) +1. (x2cm,)+1 is stored. l
Processing of c-dot line is X. -XZc is "1",
"o" between X2o and X6, "1" after Xo,
FIFO memory beauty is (X,.)+1. (X,)+t,
Xo+1 is stored. In addition, the n value of the 1-'O detection counter is 3, which is odd N, lo, and the difference from the dot line is 1+
1'', the comparison calculation control circuit n determines that the LC dot try/process is abnormal, and the FIFO memory 19, F
Compare the values of IFO memo + 722. =
1XIC-1±21→determined as normal), determines that Xc is an isolated point, sets the value of Xc+1 to the drawing memory address counter 4, reads it sequentially from the drawing memory 6,
The υ1-0 detection circuit 7 inverts the contents and writes them into the drawing memory 6 according to instructions from the comparison calculation control circuit B.

As a result, after Xc of the slc dot line, O'' is the correct result.Next, move on to processing the 'C-N dot line, and between X1cm1-1 and 2c+1 is 1''X2
(+1-X3゜+1 is '''S x3(+1
"4 (+1 is 1")

After X, the drawing memory 6 is written as °0'' and 4c+
1. The value of the 1-&O detection counter 21 is 4, an even number, and 1. Since the value of the 1-hO detection counter n for the dot line is 3 and the difference is +1, the comparison calculation control circuit n determines that the processing of the 'c+1 dot line is normal and proceeds to the processing of the next dot line.

Similarly, if the 1-0 detection counter value of the dot line being processed is an odd number, it is judged as abnormal, and the FIFO memory 1
An isolated point is determined by comparing each address value of 9 and FIFO memory, and basically the contents of the drawing memory 6 are read out from the address value of the minimum value, inverted, and written to the drawing memory 6. Further, even if the 1→0 detection counter value is an even number, if the 1→0 detection counter value of the next dot line is 0, it is determined that there is an abnormality, and that dot line is reprocessed.

Through the above processing, the figure α is filled in at high speed. When this filling process is completed, the filled figure α is transferred to the video memory and printed.

Effects of the Invention As explained above, the present invention provides 1 dot line for each dot line.
→By configuring a two-point fill method control circuit with a 0 detection circuit, its counter, and a FIFO memory that stores the address values of changing points from 1 to 40, it can process the filling of shapes without intersections at high speed. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is an example for explaining the present invention, in which (1) shows a polygon α, (2) shows an example of simply filling in using the two-point filling method, and (3) is for explanation of the present invention, and indicates explanatory expressions (dot lines, etc.). FIG. 2 is a block diagram showing an embodiment of the present invention. 1... A drawing control unit that draws the drawing memo IJK figure, 2... A timing control unit for the entire control circuit, 3.
...Set data switching gate to drawing memory address counter, 4...Drawing memory address counter, 5
. . . Data switching gate to drawing memory, 6 . . Drawing memory, 7 . . 1-40 detection circuit, 8 . . X coordinate register, 9 . . . Comparison control circuit, 11...Y coordinate register, 12...Y coordinate counter, 13°15, 16.17.18...gate, 14...video memory, 19°head...drawing memory address FIFO memory for value storage, 21°n...1→0
Detection number counter, n...Comparison/arithmetic control circuit section

Claims (1)

[Claims] In the two-point fill control method of a graphic processing device, 1 → 0 for each dot line read from the drawing memory
a detection circuit for detecting a transition to , a counter for storing the number of detections by this detection circuit, a FIFO memory for storing an address value of a change point from 1 to 0 read from the drawing memory, and the drawing memory. It is equipped with a circuit for detecting the first and last dot line where "1" exists in the space of 1, and it is possible to recognize the coordinates of the contact points and the coordinates of the vertices of the polygon with respect to the horizontal scan of the drawn circle, and it is possible to recognize the coordinates of the points of contact and the coordinates of the vertices of the polygon with respect to the horizontal scan of the drawn circle. , a figure filling circuit characterized by being able to process filling in a polygon drawn frame at high speed.