JPS61111257U - - Google Patents
Info
- Publication number
- JPS61111257U JPS61111257U JP19446484U JP19446484U JPS61111257U JP S61111257 U JPS61111257 U JP S61111257U JP 19446484 U JP19446484 U JP 19446484U JP 19446484 U JP19446484 U JP 19446484U JP S61111257 U JPS61111257 U JP S61111257U
- Authority
- JP
- Japan
- Prior art keywords
- synchronizing signal
- separation circuit
- base
- point
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案に係る同期信号分離回路の一実
施例を示す回路図、第２図は本考案を適用したテ
レビジヨン受像機を示すブロツク図、第３図は従
来の同期信号分離回路を示す回路図、第４図は一
般的同期信号分離回路の動作を説明するための説
明図、第５図は従来回路の誤動作を説明するため
の説明図である。
２，４，６，７，８，９……抵抗、１１……ダ
イオード、２３……水平ブランキングパルス、Ｑ
１，Ｑ２……トランジスタ。
Fig. 1 is a circuit diagram showing an embodiment of the sync signal separation circuit according to the present invention, Fig. 2 is a block diagram showing a television receiver to which the invention is applied, and Fig. 3 is a circuit diagram showing a conventional sync signal separation circuit. FIG. 4 is an explanatory diagram for explaining the operation of a general synchronizing signal separation circuit, and FIG. 5 is an explanatory diagram for explaining the malfunction of the conventional circuit. 2, 4, 6, 7, 8, 9...Resistance, 11...Diode, 23...Horizontal blanking pulse, Q
1 , Q2 ...Transistor.
Claims (1)
像信号が供給され、エミツタが基準電位点に接続
されてそのコレクタより同期信号を出力する同期
分離用トランジスタと、このトランジスタのベー
スにダイオードを介して水平周期のクランプパル
スを入力する手段を具備し、ブランキング期間を
除いて前記トランジスタのベース点電位を制御す
るようにしたことを特徴とする同期信号分離回路
。 A video signal including a synchronizing signal is supplied to the base via a capacitor, the emitter is connected to a reference potential point, and the collector outputs a synchronizing signal. 1. A synchronizing signal separation circuit, comprising means for inputting a clamp pulse of 1, and controlling a base point potential of the transistor except during a blanking period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19446484U JPS61111257U (en) | 1984-12-24 | 1984-12-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19446484U JPS61111257U (en) | 1984-12-24 | 1984-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61111257U true JPS61111257U (en) | 1986-07-14 |
Family
ID=30751917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19446484U Pending JPS61111257U (en) | 1984-12-24 | 1984-12-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61111257U (en) |
-
1984
- 1984-12-24 JP JP19446484U patent/JPS61111257U/ja active Pending
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