JPS61111004A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPS61111004A JPS61111004A JP23272384A JP23272384A JPS61111004A JP S61111004 A JPS61111004 A JP S61111004A JP 23272384 A JP23272384 A JP 23272384A JP 23272384 A JP23272384 A JP 23272384A JP S61111004 A JPS61111004 A JP S61111004A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- oscillation
- resistor
- input terminal
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は発振回路、特に相補型MO8FET で構成
する発振回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation circuit, and more particularly to an oscillation circuit constituted by complementary MO8FETs.
従来、電子時計等に使用している相補型MO8FET
で構成した発振回路は、電源印加後の見損安定までの
時間即ち発振開始時間が長く製造工程上回路動作の検査
で発振周波数の調整に時間が費やされてい次。一方、電
子時計の長寿命化にLり発振回路の低電力化が進み、ま
すます発振開始時間が長くなる傾向になってきている。Complementary MO8FET conventionally used in electronic watches, etc.
The oscillation circuit configured with the above has a long time to stabilize after power is applied, that is, it takes a long time to start oscillation, and during the manufacturing process, time is wasted adjusting the oscillation frequency during circuit operation inspection. On the other hand, as the lifespan of electronic watches has been lengthened, the power consumption of L-oscillation circuits has been reduced, and the oscillation start time is becoming longer and longer.
従来の発振回路の一例を!2図に示す1発振回路の入力
端チェnlt”PチャンネルMO8FET4のフロント
ゲートとNチャンネルM08FET5 のフロントゲ
ート及び抵抗3の一端に接続している。An example of a conventional oscillation circuit! The input end of the oscillation circuit shown in FIG. 2 is connected to the front gate of the P-channel MO8FET4, the front gate of the N-channel MO8FET5, and one end of the resistor 3.
PチャンネルMO8FET4 のソースは抵抗1を介
して、バックゲートは直接に電源vDDにそれぞれ接続
している。NチャンネルMO8FET5のソースは抵抗
2を介して、バックゲートは直接に電源Vs s (=
OV ) ニ接HシテIts ルー P f ヤンネ/
’MO8FET4のドレインはNチャンネルMO8FE
T5のドレインと抵抗3の他端にそれぞれ接続しており
、この接続点全発振回路の出力端子0utlとする。The source of the P-channel MO8FET4 is connected via the resistor 1, and the back gate is directly connected to the power supply vDD. The source of the N-channel MO8FET5 is connected via the resistor 2, and the back gate is directly connected to the power supply Vs s (=
OV) Double H Shite Its Lou P f Janne/
'The drain of MO8FET4 is N-channel MO8FE
It is connected to the drain of T5 and the other end of the resistor 3, respectively, and this connection point is assumed to be the output terminal 0utl of the total oscillation circuit.
入力端子In1.出力端子0UTI間に水晶振動子9金
接続している。Input terminal In1. A 9-karat gold crystal oscillator is connected between the output terminal 0UTI.
以上のように接続されt従来の発振回路においては、P
チャンネルMO8FET4及びNチャンネル間08FE
’l’5 のそれぞれのソース側に接続された抵抗1
,2は、基板バイアス効果に工り遷移領域(Pチャンネ
ルMO8FET4 あるいはNチャンネル式1(J8
FET5がON l、ている領域)におけるそれぞれ
のしきい値電圧の絶対値を高くシ、発振時の低電力化に
有効な手段となっているが、電源印加時には発振安定ま
での時間が長くなるという欠点金有している。In the conventional oscillation circuit connected as above, P
08FE between channel MO8FET4 and N channel
Resistor 1 connected to each source side of 'l'5
, 2 is a transition region (P-channel MO8FET4 or N-channel MO8FET 1 (J8
This is an effective means of reducing power consumption during oscillation by increasing the absolute value of each threshold voltage in the region where FET 5 is ON, but it takes a long time to stabilize oscillation when power is applied. It has a drawback.
〔発明が解決しようとする問題点〕
本発明の目的は、発振開始時間が短く、発振時には低電
力消費である発振回路を提供するものである。[Problems to be Solved by the Invention] An object of the present invention is to provide an oscillation circuit that has a short oscillation start time and consumes low power during oscillation.
本発明に工れば、纂1の抵抗、第1のPチャンネルMO
8FETのソース・ドレイン間、第1のNチャンネルM
O8FETのソース・ドレイン間および第2の抵抗が厘
列に接続されて構成される増幅器と、この増幅器の入・
出力間に発振素子を含んで接続され九帰還回路と、第1
の抵抗にソース・ドレイン間が並列に接続される第2の
PチャンネルMO8FET と、第2の抵抗にソース・
ドレイン間が並列に接続される第2のNチャンネルMO
8FET と、第2のPチャンネルおよびNチャンネル
MO8FET t−発振開始時に導通せしめる手段とを
有する発振回路を得る。According to the present invention, the first resistor, the first P-channel MO
Between the source and drain of 8FET, the first N-channel M
An amplifier configured by connecting the source and drain of an O8FET and a second resistor in series, and the input and output terminals of this amplifier.
A nine feedback circuit including an oscillation element is connected between the outputs, and a first
A second P-channel MO8FET whose source and drain are connected in parallel to the resistor, and a source and drain connected to the second resistor.
a second N-channel MO whose drains are connected in parallel;
An oscillation circuit is obtained having a second P-channel MO8FET and a second P-channel MO8FET and means for making the N-channel MO8FET conductive at the start of oscillation.
以下、本発明全図面金参照してより詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to all drawings.
纂1図は本発明の一実施例であり、第2図と同じ箇所は
同一符号を付しである。第2図奔念云亡Iに示した従来
の回路に、さらに入力端チェn2とPチャンネルお工び
NチャンネルMO8FET6お工び7とインバータ8を
有しており1この入力端チェn2はNチャンネルMO8
FET7 のフロントゲートとインバーン80入力に
接続され、インバータ8の出力[PチャンネルMO8F
ET6 のフロントゲートに接続されている。Pチャ
ンネルMO8FET6(7)ソース及びバックゲートハ
電源vDDにドレインはPチャンネルMO8FET4
のソースに接続されて参り、NチャンネルMO8FE
T7 のソースとバックゲートは電源V3.(=OV
) に接続され、ドレイン1jNチヤンネルMO8F
ET5のソースに接続されている。Figure 1 shows an embodiment of the present invention, and the same parts as in Figure 2 are given the same reference numerals. The conventional circuit shown in FIG. Channel MO8
It is connected to the front gate of FET7 and the input of Inburn 80, and the output of inverter 8 [P channel MO8F
Connected to the front gate of ET6. P-channel MO8FET6 (7) source and back gate are connected to power supply vDD and drain is P-channel MO8FET4
N-channel MO8FE
The source and back gate of T7 are connected to the power supply V3. (=OV
) connected to the drain 1jN channel MO8F
Connected to the source of ET5.
かかる本発明の一実施例においては、PチャンネルMO
8FET6 及びNチャンネルMO8FET7のフロ
ントゲートは、入力端チェn2に印加される入力信号に
エリON、OFF となるため、電源印加時に入力端チ
ェn2に加わる信号にノ1イレペル(電位として高い電
圧)を与えるとPチャンネルMO−8FET6及びNチ
ャンネルMO8FET7 がONになり抵抗1.2の
両端を短絡する。このことに工り抵抗1,2に前述の基
板バイアス効果がなくなり発振安定までの時間金短くす
ることができる。In one embodiment of the present invention, the P-channel MO
The front gates of 8FET6 and N-channel MO8FET7 are turned ON and OFF by the input signal applied to the input chain n2, so when power is applied, the front gates of the N-channel MO8FET7 apply a high voltage to the signal applied to the input chain n2. When this is applied, P-channel MO-8FET6 and N-channel MO8FET7 are turned on, shorting both ends of resistor 1.2. This eliminates the aforementioned substrate bias effect on the machined resistors 1 and 2, making it possible to shorten the time required for oscillation to stabilize.
発掘状態が安定となり几ところで入力端子In2にロウ
レベル(電位として低い電圧)を与えることにエリ、P
チャンネルMO8FET6 及びNチャンネルMO8
FET7がOFFとなりPチャンネルN幻−8FET4
及びNチャンネルMO8FET5のそれぞれのソース側
に接続された抵抗1.2は基板バイアス効果にLD遷移
領域におけるそれぞれのしへい値電圧の絶対fiitt
−高くし、@蚤時の低消費電力化がはかれる。When the excavation state became stable, Eri and P applied a low level (low voltage as potential) to the input terminal In2.
Channel MO8FET6 and N channel MO8
FET7 turns OFF and P channel N illusion-8 FET4
A resistor 1.2 connected to the source side of each of the N-channel MO8FETs 5 and 5 is connected to the absolute fiitt of each threshold voltage in the LD transition region due to the body bias effect.
- It is possible to increase the cost and reduce power consumption during @flea operation.
以上、説明したように本発明に工れば発振安定までの時
間を短くし低電力化も可能でありその効果は多大である
。As described above, if the present invention is implemented, it is possible to shorten the time until oscillation stabilization and reduce power consumption, which has great effects.
第1図は本発明の一実施例による回路図、第2図は従来
の発振回路の回路図である。
1,2.3・・・・・・抵抗、4.6・・・・・・Pチ
ャンネルM(JSFET、 5. 7・・・・・・Nチ
ャンネルMO8FET。
8・・・ インバータ、■。1,1n2・・・・・・入
力端子、Uutl・・・・・出力端子、9・・・・・・
水晶振動子。
代理人 弁理士 内 原 晋′;ゞ−′7゛\(
r、っ
X二一FIG. 1 is a circuit diagram according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional oscillation circuit. 1, 2.3... Resistor, 4.6... P channel M (JSFET, 5. 7... N channel MO8FET. 8... Inverter, ■.1 ,1n2...Input terminal, Uutl...Output terminal, 9...
Crystal oscillator. Agent Patent Attorney Susumu Uchihara';ゞ-'7゛\(
r, x21
Claims (1)
タのソース・ドレイン間と、第1のNチャンネル電界効
果トランジスタのドレイン・ソース間と第2の抵抗とが
直列接続され、前記第1のPチャンネルおよびNチャン
ネル電界効果トランジスタのゲート共通接続点を入力端
とし、前記PチャンネルおよびNチャンネル電界効果ト
ランジスタのドレイン共通接続点を出力端とする増幅器
と、該増幅器の前記入出力端間に発振素子を含んで接続
された帰還回路と、前記第1の抵抗に並列に接続された
第2のPチャンネル電界効果トランジスタと、前記第2
の抵抗に並列に接続された第2のNチャンネル電界効果
トランジスタと、前記第2のPチャンネルおよびNチャ
ンネル電界効果トランジスタを発振開始時に導通せしめ
る手段とを具備したことを特徴とする発振回路。The first resistor, the source-drain of the first P-channel field effect transistor, the drain-source of the first N-channel field-effect transistor, and the second resistor are connected in series, and the first P-channel field effect transistor is connected in series with the second resistor. an amplifier whose input terminal is the common connection point of the gates of the channel and N-channel field effect transistors, and whose output terminal is the common connection point of the drains of the P-channel and N-channel field effect transistors; and an oscillation element between the input and output terminals of the amplifier. a second P-channel field effect transistor connected in parallel to the first resistor;
An oscillation circuit comprising: a second N-channel field effect transistor connected in parallel to the resistor; and means for rendering the second P-channel and N-channel field effect transistors conductive at the start of oscillation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23272384A JPS61111004A (en) | 1984-11-05 | 1984-11-05 | Oscillation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23272384A JPS61111004A (en) | 1984-11-05 | 1984-11-05 | Oscillation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61111004A true JPS61111004A (en) | 1986-05-29 |
Family
ID=16943773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23272384A Pending JPS61111004A (en) | 1984-11-05 | 1984-11-05 | Oscillation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61111004A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171644A (en) * | 2009-01-21 | 2010-08-05 | Oki Semiconductor Co Ltd | Constant current driven oscillating circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5824207A (en) * | 1981-08-05 | 1983-02-14 | Oki Electric Ind Co Ltd | Oscillator type oscillating circuit |
-
1984
- 1984-11-05 JP JP23272384A patent/JPS61111004A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5824207A (en) * | 1981-08-05 | 1983-02-14 | Oki Electric Ind Co Ltd | Oscillator type oscillating circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171644A (en) * | 2009-01-21 | 2010-08-05 | Oki Semiconductor Co Ltd | Constant current driven oscillating circuit |
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