JPS61110067A - Ground-fault location system for parallel two-circuit - Google Patents

Ground-fault location system for parallel two-circuit

Info

Publication number
JPS61110067A
JPS61110067A JP23176884A JP23176884A JPS61110067A JP S61110067 A JPS61110067 A JP S61110067A JP 23176884 A JP23176884 A JP 23176884A JP 23176884 A JP23176884 A JP 23176884A JP S61110067 A JPS61110067 A JP S61110067A
Authority
JP
Japan
Prior art keywords
line
fault point
bus terminal
zero
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23176884A
Other languages
Japanese (ja)
Other versions
JPH0634023B2 (en
Inventor
Tokuo Emura
徳男 江村
Masayasu Takeuchi
雅靖 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP23176884A priority Critical patent/JPH0634023B2/en
Publication of JPS61110067A publication Critical patent/JPS61110067A/en
Publication of JPH0634023B2 publication Critical patent/JPH0634023B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Locating Faults (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE:To locate the distance to a fault point from a bus terminal of its own at a high accuracy, by performing a computation for the location between the bus terminal of its own and a branch and between the branch and the opponent bus terminal separately by a specified formula from zero-phase currents flowing through circuits in case of a ground-fault of one line in a system having branches from the circuits of a parallel two-circuit power transmission line. CONSTITUTION:The case is divided as follows, where a ground-fault point exists between the bus terminal of its own and the branches and does between the branches and the opponent bus terminal. The distance X (0<=x<=1) to the fault point with each section put at 1, is determined by the formula I (I01 and I02 is zero-phase impedance of each circuit 0<=x<=1 Z0a, Z0b, Z0c: line impedance) for the fault point existing between the bus terminal of its own and the branches or by the formula II for the fault point existing between the branches and the opponent bus terminal to locate the distance to the fault point.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は高抵抗接地系におけろ平行2回線地絡故障点
標定方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a parallel two-circuit ground fault fault location method in a high-resistance grounding system.

(従来の技術) 平行2回線送電線の地絡故障に対する故障点の標定には
一般的に零相電流分流比による故障点標定方式が考えら
れている。この故障点標定方式による原理について$2
図乃至第3図に基づきまず説明する。
(Prior Art) A fault point locating method using a zero-sequence current shunt ratio is generally considered for locating a fault point for a ground fault in a parallel two-circuit power transmission line. About the principle of this failure point locating method $2
First, explanation will be given based on FIGS. 3 to 3.

第2図は平行2回線の系統図(単相表現)を示し、A、
Bは自端側(標定装置設置点側)、相手端側の各母線、
II、、2Lは母線人、B間に設けられた平行する各回
線である。いま図は回、l1ILの個所Fで1線地絡故
障が発生したものとしている。
Figure 2 shows a system diagram (single phase representation) of two parallel lines, A,
B is each bus line on the own end side (location device installation point side) and the other end side,
II, , 2L are parallel lines provided between bus lines B and B. The figure now assumes that a one-wire ground fault has occurred at point F of l1IL.

そして上記故障に対する対称座標法から得られる零相等
価回路は第3図のよう1こ表わされる。ここで工は回線
の全長を1としたときの自端から故障点F”までの距1
4K(割合)、ioは各回線の零相インピーダンス、i
ol、La2は各回線の零相電流、fdrは故障点零相
電流であり、これらは下記の関係式で表現できる。
The zero-phase equivalent circuit obtained from the symmetric coordinate method for the above-mentioned fault is expressed as shown in FIG. Here, when the total length of the line is 1, the distance from the own end to the fault point F is 1.
4K (ratio), io is the zero-sequence impedance of each line, i
ol and La2 are the zero-sequence currents of each line, and fdr is the fault point zero-sequence current, which can be expressed by the following relational expression.

fof==io1+foz         fl)x
Za Io1=(1+ 1−x )ZoIo2   +
21(11,+21式より 1o1=”7’jof、 1az=テIof  (31
(31式より が得、6れ、前(41,(51式はそれぞれ回線IL、
2Lの自端側から故障点までの距離を与える。
fof==io1+foz fl)x
ZaIo1=(1+1-x)ZoIo2+
21 (11, +21 formula, 1o1=”7'jof, 1az=teIof (31
(Formula 31 is obtained, 6 is, before (41, (Formula 51 is line IL, respectively)
Give the distance from the own end of 2L to the failure point.

ところで、第4図のように平行2回線の各回線より分岐
lsI L’、 2L’を設けろ系統において、DB間
で1線地絡故障が発生した場合の零相等価回路を第5図
で示す。
By the way, Figure 5 shows the zero-phase equivalent circuit when a one-wire ground fault occurs between DB in a system in which branches lsI L' and 2L' are provided from each line of two parallel lines as shown in Figure 4. .

ここで、λF間、Dr間の距離(割合)をそれぞれX+
、にとすれば、 Vf ==vg −I 02 Zoa (2−xt )
 Zob X o3    (sl?f=?o−I’o
、Zoa−xtZob(io1+ioz −1as) 
 (71?f=?o−1oz Zoa−2(1oz−T
”o3) 2oc但し 0≦x1≦1 0≦X!≦1 ?f:地終点の対地電圧 tO:自端零相電圧 Zoa:AD間の線路インピーダンス zob: D B間の線路インピーダンス20c:DC
間の線路インピーダンス が成立する。前+61 、 +71 、 +81式をx
lについて解くと、となる。1豐、x4の関係は xt (ZOa−)−ZQb )=ZOa+xr Zo
bとなるからxlは で表わされる。ここで(9)式と前(4)式を比較する
と共通する部分は t02 I01+IO2 のみであり、従って前(4)式は(9)式に比べて誤差
が生じることになる。これは前+41.151式による
場合が地絡故障点Fへの電流経絡として人→IL−Fと
、人→2t−B→1L→Fの2経路であるのに対し、分
岐を有する系統では、この2経路のほかに人→2L→D
−+C4D→1L→Fの電流経路が加わるためである。
Here, the distance (ratio) between λF and Dr is X+
, then Vf ==vg -I 02 Zoa (2-xt)
Zob X o3 (sl?f=?o-I'o
, Zoa-xtZob(io1+ioz-1as)
(71?f=?o-1oz Zoa-2(1oz-T
”o3) 2ocHowever, 0≦x1≦1 0≦X!≦1 ?f: Voltage to ground at the end point tO: Self-end zero-sequence voltage Zoa: Line impedance between AD zob: Line impedance between D and B 20c: DC
A line impedance between the two is established. x the previous +61, +71, +81 formulas
Solving for l yields. 1, the relationship between x4 is xt (ZOa-)-ZQb)=ZOa+xr Zo
b, so xl is expressed as. Here, when formula (9) is compared with formula (4), the only common part is t02 I01+IO2, and therefore formula (4) has an error compared to formula (9). This is because in the case of the previous +41.151 formula, the current meridian to the ground fault point F is two routes: person → IL-F and person → 2t-B → 1L → F, whereas in a system with branches, , in addition to these two routes, people → 2L → D
This is because a current path of -+C4D→1L→F is added.

(@明が解決しようとする問題点) この発明は前述のように平行2回線の各回線に分岐線を
もつ系統では従来の零相電流分流比による方式をそのま
ま適用すると誤まった標定をしてしまうことに着目し、
この誤差を除去して故障点までの距噛を高講度で標定す
ることを目的とする。
(Problem that @Akira is trying to solve) As mentioned above, in a system where each line of two parallel lines has a branch line, if the conventional method using the zero-sequence current shunt ratio is applied as is, incorrect orientation will occur. Focusing on the fact that
The purpose is to remove this error and locate the distance to the failure point with a high degree of accuracy.

(問題点を解決するための手段) この発明による方式は地絡故障点が人り間に存在する場
合と、DB間に存在する場合の2つに分け、それぞれの
区rJtlを1としたときのその故障点までの距離X(
但し0≦工≦1)を次式によって求めることを特徴とす
る。即ち (但し故障点がAD間に存在する場合)(但し故障点が
DB間に存在する場合)なお、前(1G、(ロ)式で、
故障区間が何れに存在するかはαG、(ロ)式で求まる
答をそれぞれXAD、 XDBとすればAD間のとき0
≦XAD≦1 、 XDB≦0゜DB間のとき1≦xA
D、0≦xDB≦1となるので、XAD 、 XDBを
比較することにより判別できる。
(Means for solving the problem) The method according to the present invention is divided into two cases: a case where the ground fault fault point exists between people and a case where it exists between DBs, and when rJtl of each section is set to 1. The distance to that failure point X (
However, it is characterized in that 0≦work≦1) is determined by the following equation. In other words, (however, if the failure point exists between AD) (however, if the failure point exists between DB), in the previous (1G, (b) equation),
αG is where the failure zone exists, and if the answers found by equation (b) are XAD and XDB, then 0 when between AD.
When ≦XAD≦1, XDB≦0゜DB, 1≦xA
Since D, 0≦xDB≦1, it can be determined by comparing XAD and XDB.

また、故障点が回線1Lか2Lかは、1Lの場合は上記
によって、2Lの場合は1≦XAD、  j≦XDBと
なるので1Lの故・陣でないことが判断できるし、この
場合式中の101とI”02を入替えて判別できるもの
である。
Also, to determine whether the failure point is line 1L or 2L, in the case of 1L, the above applies, and in the case of 2L, 1≦XAD, j≦XDB, so it can be determined that it is not the fault of 1L, and in this case, the equation in the equation This can be determined by replacing 101 and I''02.

(実施例) 以下この発明の方式を用いた具体的実施例を第1図に示
す。
(Example) A specific example using the method of the present invention is shown in FIG. 1 below.

IL’、2L’は分岐線である。IL' and 2L' are branch lines.

回線IL、2Lの自端側に設けた変流器ICT。Current transformer ICT installed at the own end of lines IL and 2L.

2CTにより回線単位の零相電流io1.iozを得ろ
2CT, the zero-sequence current io1. Get the ioz.

IAX、2AXは前記零相電流fot、 fozを適当
な値の電圧に変換する補助変流器、AFは系統から得ら
れる零相YIL流情報に含まれる高調波成分をカットし
、折返し誤差を除去するために設けられるアナログフィ
ルタである。VHはサンプルホールド回路であり、前記
零相電流情報を制御回路CONから指令に基き例えば1
サイクル中12回(60°間隔)の同時刻サンプリング
を行いそのサンプル値を保持する。MPXは前記サンプ
ル値を順次切替えて出力するマルチプレクサ、¥Dは前
記アナログのサンプル値をデジタル量に変換するAD変
換器である。CPUは前記デジタル情報を記憶すると同
時に所定の演算を行うマイクロプロセッサ等の演算装置
、0UTi!出力回路である。なお、MPX 、 A/
D 。
IAX and 2AX are auxiliary current transformers that convert the zero-sequence currents fot and foz into appropriate voltage values, and AF cuts harmonic components included in the zero-sequence YIL flow information obtained from the grid and eliminates aliasing errors. This is an analog filter provided for the purpose of VH is a sample hold circuit, which stores the zero-phase current information, for example, by 1 based on a command from the control circuit CON.
Simultaneous sampling is performed 12 times (at 60° intervals) during the cycle and the sampled values are held. MPX is a multiplexer that sequentially switches and outputs the sample values, and ¥D is an AD converter that converts the analog sample values into digital quantities. The CPU is an arithmetic device such as a microprocessor that stores the digital information and simultaneously performs predetermined arithmetic operations, 0UTi! This is an output circuit. In addition, MPX, A/
D.

CPUはS/l(同様制御回路CONからの指令に基き
所定の動作を行う。
The CPU performs predetermined operations based on commands from the S/I (similarly, the control circuit CON).

而して、任意の回線で地絡故障が発生したとすると各回
線に零相電流io1.iozが流れるのでこれらがサン
プリングデータとしてCPUに記憶されろ。
Therefore, if a ground fault occurs in any line, a zero-sequence current io1. ioz will flow, so these should be stored in the CPU as sampling data.

そしてCPUでサンプリングデータより基本波成分が抽
出される。ここで回線長(λB間)及び各回線と分岐線
の線路インピーダンスは既知であるから先の(IG、(
ロ)式にしたがって演算する。この演算出力は故障点ま
での距離Xにほかならない。
Then, the fundamental wave component is extracted from the sampling data by the CPU. Here, the line length (between λB) and line impedance of each line and branch line are known, so (IG, (
b) Calculate according to the formula. This calculation output is nothing but the distance X to the failure point.

(発明の効果) 以上のようにこの発明によれば高抵抗接地系平行2回線
送電線において自端と相手端間に分岐線をもつ系統に適
用できるほか、原理的に誤差がなく高精度の故障点標定
か実現できる効果を奏する。
(Effects of the Invention) As described above, the present invention can be applied to a high-resistance grounded parallel two-circuit power transmission line that has a branch line between its own end and the other end, and can also be applied to systems with no errors in principle and high precision. This has the effect of locating the failure point.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すブロック線図、第2図は
平行2回線送amの単線系統図、第5図は故障時の零相
等価回路図、第4図は本発明方式を説明するための分岐
線を有する平行2回線の単線系統図、第5図は故障時の
零相等価回路図である。 1L、2L・・・各回線 IL’、2L’・・・各分岐線 AP・・・アナログフィルタ S/)(・・・サンプルホールド回路 MPX・・・マルチプレクサ CON・・・制御回路 4/D・・・アナログデジタル変換器 cpσ・・・演算装置
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a single line system diagram of parallel two-line AM, Fig. 5 is a zero-phase equivalent circuit diagram at the time of failure, and Fig. 4 is a diagram showing the system of the present invention. A single-line system diagram of two parallel circuits with branch lines for explanation, and FIG. 5 is a zero-phase equivalent circuit diagram at the time of failure. 1L, 2L...Each line IL', 2L'...Each branch line AP...Analog filter S/) (...Sample hold circuit MPX...Multiplexer CON...Control circuit 4/D... ...Analog-to-digital converter cpσ...Arithmetic unit

Claims (1)

【特許請求の範囲】 1、高抵抗接地系平行2回線送電線であつて各回線より
分岐する分岐線を有する系統において、1線地絡時に流
れる各回線の零相電流を入力とし、自母線端と分岐線間
の標定を ▲数式、化学式、表等があります▼ に、及び分岐線と相手母線端間の標定を ▲数式、化学式、表等があります▼ 但し 0≦X≦1 ■_0_a、■_0_b、■_0_c:線路インピーダ
ンスにしたがつて演算し、この演算出力を自母線端から
故障点までの距離に標定してなる平行2回線地絡故障点
標定方式。
[Scope of Claims] 1. In a system that is a high-resistance grounded parallel two-circuit power transmission line and has branch lines branching from each line, the zero-sequence current of each line that flows when one line is grounded is input, and The orientation between the end and the branch line is ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ The orientation between the branch line and the end of the other bus line is ▲ The orientation is ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ However, 0≦X≦1 ■_0_a, ■_0_b, ■_0_c: Parallel two-line ground fault fault point locating method that calculates according to the line impedance and locates the calculated output as the distance from the own bus line end to the fault point.
JP23176884A 1984-11-02 1984-11-02 Parallel two-circuit ground fault fault location method Expired - Lifetime JPH0634023B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23176884A JPH0634023B2 (en) 1984-11-02 1984-11-02 Parallel two-circuit ground fault fault location method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23176884A JPH0634023B2 (en) 1984-11-02 1984-11-02 Parallel two-circuit ground fault fault location method

Publications (2)

Publication Number Publication Date
JPS61110067A true JPS61110067A (en) 1986-05-28
JPH0634023B2 JPH0634023B2 (en) 1994-05-02

Family

ID=16928721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23176884A Expired - Lifetime JPH0634023B2 (en) 1984-11-02 1984-11-02 Parallel two-circuit ground fault fault location method

Country Status (1)

Country Link
JP (1) JPH0634023B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200077A (en) * 1987-02-16 1988-08-18 Fuji Electric Co Ltd Trouble point locating system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200077A (en) * 1987-02-16 1988-08-18 Fuji Electric Co Ltd Trouble point locating system

Also Published As

Publication number Publication date
JPH0634023B2 (en) 1994-05-02

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