JPS61107721A - Si substrate provided with iii-v compound single crystal thin film and manufacture thereof - Google Patents

Si substrate provided with iii-v compound single crystal thin film and manufacture thereof

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Publication number
JPS61107721A
JPS61107721A JP22801084A JP22801084A JPS61107721A JP S61107721 A JPS61107721 A JP S61107721A JP 22801084 A JP22801084 A JP 22801084A JP 22801084 A JP22801084 A JP 22801084A JP S61107721 A JPS61107721 A JP S61107721A
Authority
JP
Japan
Prior art keywords
thin film
single crystal
iii
crystal thin
film layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22801084A
Other languages
Japanese (ja)
Inventor
Masaki Inada
稲田　雅紀
Kazuo Eda
江田　和生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22801084A priority Critical patent/JPS61107721A/en
Publication of JPS61107721A publication Critical patent/JPS61107721A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02466—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To enable forming of high quality GaAs or GaP on an Si substrate by removing the interface charge, the site allocation and the lattice unmatching between a formed III-V compound and a ground diamond construction material. CONSTITUTION:Superlattice construction thin film multilayer constructions 5, 6 consisting of Ge-Si system two composition solid solution single crystal thin films are epitaxially grown on an Si (211) substrate 1 wherein an oxide film on the surface is removed. In this case, the upper construction 6 which has smaller lattice constant is set at the mean lattice constant of the lower construction 5. Similarly, superlattice constructions 7-10 are formed. In this case, lattice unmatching is reduced toward an upper layer and lattice constant is increased toward an upper layer. Then, a superlattice construction thin film layer 11 consisting of a single crystal thin film layer of Ge-Si system solid solution and Sn-Ge system solid solution and wherein the mean lattice constant is matched to the lattice constant of Ge is formed. A superlattice construction thin film 12 consisting of III-V compound which has lattice matching with GaAs and a III-V compound single crystal thin film 13 which has lattice matching with GaAs are formed on the layer 11.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、■−■化合物単結晶薄膜をそなえたＳｉ基板
とその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a Si substrate provided with a single crystal thin film of a ■-■ compound and a method for manufacturing the same.

（従来例の構成とその問題点） 単結晶Ｇａ、Ｓｉの上に、それぞれ単結晶ＧａＡｓ、Ｇ
ａＰをエピタキシャル成長させる試みは、それらの２つ
の材料の格子不整合が、それぞれ、０．１％、０．３７
％と小さく　、ＧａＡｓ、ＧａＰのバンドギャップが、
それぞれＧｅ、Ｓｉより大きいため、それらをエミッタ
とするヘテロバイポーラトランジスタとして有望である
ことの他に、形成されるＧａＡｓ、ＧａＰを用いる多く
の産業上の有用な用途があることから、古くから数多く
なされてきた。しかし、この系では■−■化合物同士の
エピタキシーと違って、格子整合だけでは解決できない
難しい問題があり、反位相構造、双晶、転位などの欠陥
が極めて多く生じ、結晶成長はうまくいかなかった。近
年、その原因がかなり明らかになってきた。まず、１９
７８年に、極性のＧａＰ、ＧａＡｓなどのｍ−ｖ化合物
をＳｉ、Ｇｅのような非極性のダイヤモンド構造をもつ
材料の上にエピタキシャル成長させる場合には、結晶方
位によって界面にチャージが生じ（たとえば〔１ｏｏ）
　、　（ｔｏ））、このチャージは、バンド構造や結晶
成長に十分な影響を与えるだけ大きいこと、そして（１
１０）ではこのチャージが生じないため、デバイスや結
晶成長に適することが指摘された。　（Ｗ、Ａ、Ｈａｒ
ｒｉｓｏｎ　ａｔａｌ、Ｐｈｙｓ、Ｒｅｖ、８１８．４
４０２（１９７Ｂ））。(Structure of conventional example and its problems) Single crystal GaAs and G on single crystal Ga and Si, respectively.
Attempts to epitaxially grow aP have shown that the lattice mismatch between the two materials is 0.1% and 0.37%, respectively.
The band gap of GaAs and GaP is as small as %.
Since they are larger than Ge and Si, they are promising as hetero-bipolar transistors using them as emitters, and there are many useful industrial applications using GaAs and GaP, which have been used for a long time. It's here. However, in this system, unlike epitaxy between ■-■ compounds, there were difficult problems that could not be solved by lattice matching alone; an extremely large number of defects such as antiphase structures, twins, and dislocations occurred, and crystal growth did not go well. . In recent years, the cause has become much clearer. First, 19
In 1978, when a polar m-v compound such as GaP or GaAs is epitaxially grown on a non-polar diamond structure material such as Si or Ge, a charge is generated at the interface depending on the crystal orientation (for example, 1oo)
, (to)), this charge is large enough to have a sufficient effect on the band structure and crystal growth, and (1
10), it was pointed out that this charge does not occur, so it is suitable for device and crystal growth. (W, A, Har
rison atal, Phys, Rev, 818.4
402 (197B)).

ついで、１９８２年に、それらのエピタキシーにおいて
は、界面チャージが生じないことだけでなく、■−■化
合物の■族および■広原子が下地のダイヤモンド構造か
らなる結晶のサイトのどこに結合するかということ（サ
イト・アロケーション）が重要となり、■族と■広原子
のサイト・アロケーションが確定されることが、深刻な
問題となっている反位相構造の発生を避けるために極め
て重要となることが指摘された。そして、界面チャージ
が生じないことと、サイト・アロケーションが確定され
ることの２つの条件が満足される結晶面として、Ｓｉ　
、　Ｇｅなどのダイヤモンド構造をとる結晶の結合サイ
トを構成する４個の結合手の１個が基板に平行に存在し
く第１図の符号１）かっ、それらのサイトが基板から上
方に向いた１個の結合手にのるサイト（第１図の符号２
）と、基板から上方に向いた２本の結合手にのるサイト
（第１図の符号３）の２種類のサイトからなる結晶面が
有望であり、その最も簡単な結晶面が第１図に示す（２
１１）結晶面であることが指摘された（Ｓ、Ｖｒｉｇｈ
ｔ　ｅｔａｌ、Ｊ。Next, in 1982, it was discovered that in these epitaxies, not only did interfacial charges not occur, but also where the ■ group and ■ wide atoms of the ■-■ compound bonded to the sites of the underlying diamond structure crystal. It has been pointed out that (site allocation) is important, and that it is extremely important to determine the site allocation of group ■ and ■ broad atoms in order to avoid the occurrence of anti-topological structure, which is a serious problem. Ta. Then, Si
, One of the four bonding hands constituting the bonding site of a crystal with a diamond structure such as Ge exists parallel to the substrate, and the site is oriented upward from the substrate. The site on the bond (number 2 in Figure 1)
) and a site that rests on two bond hands pointing upward from the substrate (number 3 in Figure 1) are promising, and the simplest crystal plane is shown in Figure 1. Shown in (2
11) It was pointed out that it is a crystal plane (S, Vright
t etal, J.

Ｖａｃ、Ｓｃｉ、Ｔｅｃｈｎｏｌ、　、２１，５３４（
１９ｇ２））。Vac, Sci, Technol, 21,534 (
19g2)).

第１図はＳｉ　、　Ｇｅあるいはそれぞれの固溶体など
のダイヤモンド構造を（１１０）方向から見た図である
。１はＳｉの結合サイトを構成する４個の結合手の中で
基板に平行となっている結合手、２は基板の下方から上
方に向かう２本の結合手にのるＳｉ結合サイト、３は基
板の下方から上方に・向かう２本の結合手にのるＳｉ結
合サイトを示す。FIG. 1 is a diagram of a diamond structure such as Si, Ge, or a solid solution of each as viewed from the (110) direction. 1 is a bond that is parallel to the substrate among the 4 bonds that make up the Si bond site, 2 is a Si bond site that is on two bonds that extend from the bottom to the top of the substrate, and 3 is a bond that is parallel to the substrate. It shows the Si bonding sites on two bonding hands going from the bottom to the top of the substrate.

この結晶面では、２種類の質的に異なるサイトからなる
ため、■族とＶ広原子が選択的にそれぞれのサイトに結
合することが期待されるわけである。そして、実際に、
Ｓｉ（２１１）基板を用いて、分子線エピタキシー法に
よりＧａＰのエピタキシャル成長を行ない、提唱した理
論が正しいことが実証された。これによって、はじめて
、Ｓｉ基板上に、反位相構造のない、鏡面をもっＧａＰ
の単結晶薄膜層が形成された。このヘテロ構造を用いて
β：９の過去最高のβ値をもつヘテロバイポーラトラン
ジスタが作られたが、この特性は、トランジスタとして
はまだ十分なものではなかった。これは反位相構造以外
の結晶欠陥がまだ多く含まれていることによる。事実１
表面には、内部欠陥の存在を示す多くの平行に走った線
状の微細構造が存在していた。しかし、この方式により
、界面チャージをなくすること、および最も深刻な問題
であった反位相構造の発生をなくすることの２つの基本
的な、重要な課題が解決されているので、反位相構造以
外の、おもに格子不整合によって生じる結晶欠陥を除去
することができれば、高品質のＧａＰ単結晶薄膜をそな
えたＳｉ基板の作製が期待できるわけである。Ｇｅの上
にＧａＡｓを形成する場合には、格子不整合はＳｉとＧ
ａＰの場合よりもはるかに小さいので、上述の結晶方位
をもつ基板を用いてＳｉ上へのＧａＰの形成を行なう場
合よりも良い結晶成長が期待できるわけであるが、Ｇｅ
の単結晶基板は表面の清浄化が難しいことが大きな問題
点であった。Since this crystal plane consists of two qualitatively different types of sites, it is expected that group Ⅰ and V broad atoms selectively bond to each site. And actually,
Using a Si(211) substrate, GaP was epitaxially grown by molecular beam epitaxy, and the proposed theory was proven to be correct. As a result, for the first time, GaP with a mirror surface without an anti-phase structure can be formed on a Si substrate.
A single crystal thin film layer was formed. Using this heterostructure, a heterobipolar transistor with the highest ever β value of β:9 was created, but this characteristic was still not sufficient for a transistor. This is because many crystal defects other than the antiphase structure are still included. Fact 1
There were many parallel linear microstructures on the surface, indicating the presence of internal defects. However, this method solves two fundamental and important problems: eliminating interfacial charges and eliminating the most serious problem, the generation of antiphase structures. If other crystal defects, mainly caused by lattice mismatch, can be removed, we can expect to produce a Si substrate with a high-quality GaP single crystal thin film. When forming GaAs on Ge, lattice mismatch occurs between Si and G.
Since it is much smaller than that of aP, better crystal growth can be expected than when forming GaP on Si using a substrate with the above-mentioned crystal orientation.
A major problem with single-crystal substrates is that it is difficult to clean the surface.

この場合、界面チャージ、サイト・アロケーション、お
よび格子整合の課題が解決さ九でも１表面の清浄化が難
しいために各種の欠陥が発生する。In this case, although the problems of interfacial charging, site allocation, and lattice matching are solved, various defects occur due to the difficulty of cleaning the surface.

一般によく用いられる（１００）　、　（１１１）や（
１１０）などのＳｉ　、　Ｇｅなどのダイヤモンド構造
を有する材料の基板では、っぎのような問題点がある。Commonly used (100), (111) and (
110) and other materials having a diamond structure, such as Si and Ge, have the following problems.

　（１００）および（１１１）基板の場合には、その上
にｍ−■化合物を形成すると界面にチャージが生じるこ
との他に、表面が同一種のサイトからなるため、■族、
■広原子のサイト・アロケーションが確定されないので
結晶成長が難かしい。これらの結晶面でサイト・アロケ
ーションの問題を解決する方法がみつかり、良い結晶成
長が行なわれれば、形成された■−■化合物を用いるデ
バイスへの適用は可能となるが、下地の非極性の材料と
の界面にチャージが生じるため、この界面を用いるデバ
イスには適しているとはいえない。（１１０）基板の場
合には、界面チャージは生じないが、■族、■広原子の
サイト・アロケーションが確定されないので、欠陥の少
ない単結晶膜の結晶成長が難かしい。（１１０）基板に
おいて、サイト・アロケーションを解決するなんらかの
方法が見つかれば、界面チャージが生じないことから、
■−■化合物材料とダイヤモンド構造をもつ材料とのへ
テロ構造を用いるデバイスや形成された■−■化合物材
料を基板として用いるデバイスなどの種々の応用がある
。これらの結晶面を用いて、ある程度の品質のＧａＡｓ
が形成されたという報告もあるが、上述のように原理的
に結晶成長が難しいことから十分なものではない。In the case of (100) and (111) substrates, in addition to the generation of charges at the interface when m-■ compounds are formed thereon, since the surfaces are composed of sites of the same type,
■Crystal growth is difficult because the site allocation of wide atoms is not determined. If a method is found to solve the site allocation problem on these crystal planes and good crystal growth is achieved, it will be possible to apply the formed ■-■ compound to devices, but the non-polar underlying material Since a charge is generated at the interface with the material, it is not suitable for devices using this interface. In the case of a (110) substrate, no interfacial charge occurs, but the site allocation of the (1) group and (1) group atoms is not determined, making it difficult to grow a single crystal film with few defects. (110) If some method is found to solve the site allocation in the substrate, interfacial charges will not occur.
There are various applications such as devices using a heterostructure of a ■-■ compound material and a material with a diamond structure, and devices using the formed ■-■ compound material as a substrate. Using these crystal planes, GaAs of a certain quality can be produced.
Although there are reports that crystals have been formed, as mentioned above, crystal growth is difficult in principle, so this is not sufficient.

また、Ｇａ’Ａｓ単結晶基板は高温であることから、安
価なＳｉ単結晶基板の上にＧａＡｓをエピタキシャル成
長しようという試みもなされてきたが、この場合には、
界面チャージ、サイト・アロケーションの問題に加えて
、　ＧａＡｓとＳｉの４．１％の大きな格子不整合の問
題が加わるので成長は一層難かしかった。Furthermore, since Ga'As single crystal substrates are at high temperatures, attempts have been made to epitaxially grow Ga'As on inexpensive Si single crystal substrates, but in this case,
In addition to interfacial charge and site allocation issues, growth was made even more difficult by the large 4.1% lattice mismatch between GaAs and Si.

（発明の目的） 本発明の目的は、形成される■−■化合物と下地のダイ
ヤモンド構造材料との界面チャージと、サイト・アロケ
ーションの問題を解決するとともに、ＧａＡｓとＳｉと
の間にある４、１％の大きな格子不整合を解決し、　Ｇ
ａＡｓを基板として用いるデバイスさらに、それらのデ
バイスとＳｉデバイスとを一体化したデバイスなどに適
用可能な、■−■化合物単結晶薄膜をそなえたＳｉ基板
および、その製造方法を提供することである。(Objective of the Invention) The object of the present invention is to solve the problems of interfacial charge and site allocation between the formed ■-■ compound and the underlying diamond structure material, and to solve the problem of site allocation between GaAs and Si. Resolving the large lattice mismatch of 1%, G
It is an object of the present invention to provide a Si substrate provided with a compound single crystal thin film and a method for manufacturing the same, which can be applied to devices using aAs as a substrate, as well as devices in which these devices and Si devices are integrated.

（発明の構成） 本発明の■−■化合物単結晶薄膜をそなえたＳｉ基板お
よびその製造方法は、Ｓｉの結合サイトを構成する４個
の結合手の１個が基板に平行に存在した結晶方位を有す
る単結晶Ｓｉ基板上に、　Ｇｅ、Ｓｉを含めて、Ｇｅ−
Ｓｉ系の２つの組成の固溶体の単結晶薄膜からなる超格
子構造薄膜層の多層構造を、超格子構造を構成する２つ
の固溶体の格子定数の平均値が、上側に位置する超格子
構造を構成する２つの固溶体の小さい方の格子定数に近
くなるようにし、かつ上部方面に段階的に大きくなり、
かつ超格子構造を構成する２つの固溶体の格子不整合が
上方向に段階的に小さくなるように形成し、その上に、
Ｇｅ−Ｓｉ系固溶体と少量のＳｎを固溶したＳｎ−Ｇｅ
系固溶体の単結晶薄膜層からなり、かつそれらの格子定
数の平均値がＧｅの格子定数に十分に格子整合する超格
子構造薄膜層を形成し、その上にＧａＡｓと格子整合す
る■−■化合物の間で構成される超格子構造薄膜層を形
成し、その上にＧａＡｓと格子整合するｍ−ｖ化合物の
単結晶薄膜層を形成した構造を有するものであり、また
その製造方法である。(Structure of the Invention) The Si substrate provided with the ■-■ compound single-crystal thin film of the present invention and the manufacturing method thereof are characterized in that one of the four bonding hands constituting the Si bonding site exists in a crystal orientation parallel to the substrate. On a single-crystal Si substrate having
A superlattice structure consisting of a single-crystal thin film of a Si-based solid solution with two compositions has a multilayer structure, and the average value of the lattice constants of the two solid solutions constituting the superlattice structure constitutes a superlattice structure located on the upper side. The lattice constant should be close to that of the smaller of the two solid solutions, and the lattice constant should gradually increase toward the top.
The superlattice structure is formed in such a way that the lattice mismatch between the two solid solutions becomes gradually smaller in the upward direction, and on top of that,
Sn-Ge containing Ge-Si solid solution and a small amount of Sn
■-■ compound that forms a superlattice structure thin film layer consisting of a single crystal thin film layer of a system solid solution and whose average value of the lattice constants is sufficiently lattice-matched to the lattice constant of Ge, and is lattice-matched to GaAs on the superlattice structure thin film layer. It has a structure in which a superlattice structure thin film layer consisting of GaAs is formed, and a single crystal thin film layer of an m-v compound lattice-matched to GaAs is formed thereon, and it is also a manufacturing method thereof.

またＳｉ（２１１）基板を用いたものであり、さらに、
■−■化合物の間で形成される超格子構造薄膜と１＋ して、ＧａＡｓ、Ａ（ＩＡｓおよびＡ（ｌｘＧａ、−ｘ
Ａｓ固溶体の間で構成される超格子構造薄膜層を用いる
ものである。Moreover, it uses a Si (211) substrate, and furthermore,
The superlattice structure thin film formed between ■-■ compounds and 1+ are GaAs, A(IAs and A(lxGa, -x
A superlattice structure thin film layer composed of As solid solutions is used.

（実施例の説明） 本発明の実施例を第２図ないし第７図に基づいて説明す
る。(Description of Embodiments) Embodiments of the present invention will be described based on FIGS. 2 to 7.

第２図は、Ｓｉ上に形成するＧｅ、Ｓｉ１−ｘ固溶体お
よびＳｎ、Ｇｅ１−Ｆ固溶体の組成と格子定数の関係お
よび実施例工ないし２に用いた超格子構造薄膜層の構成
成分の組成と格子定数との関係を示す。横軸はＸ、縦軸
ｙは格子定数を示す。１ないし７は基板側からこの順序
に形成する格子構造薄膜層を構成する２つの固溶体の組
成と格子不整合を示す。Figure 2 shows the relationship between the composition and lattice constant of the Ge, Si1-x solid solution and Sn, Ge1-F solid solution formed on Si, and the composition of the constituent components of the superlattice structure thin film layer used in Examples 2 to 2. The relationship with the lattice constant is shown. The horizontal axis represents X, and the vertical axis y represents the lattice constant. 1 to 7 indicate the composition and lattice mismatch of two solid solutions constituting the lattice structure thin film layer formed in this order from the substrate side.

第３図ないし第４図においては１は基板、１は基板、２
はＳｉバッファ層、３はＧｅ、　、、Ｓｉ、　、、の単
結晶薄膜層、４はＳｉの単結晶薄膜層、符号５ないし１
１は第２図の符号工ないし７にそれぞれ対応する超格子
構造薄膜層を示す。１２はＡＩ、　、、Ｇａ０．７Ａｓ
とＧａＡｓからなる超格子構造薄膜層、１３はＧａＡｓ
の単結晶薄膜層、　１４はＡ１１．．３Ｇａ、　、、Ａ
ｓの単結晶薄膜層を示す。In Figures 3 and 4, 1 is a substrate;
3 is a single crystal thin film layer of Ge, , Si, , , 4 is a single crystal thin film layer of Si, and symbols 5 to 1 are Si buffer layers.
Reference numeral 1 indicates superlattice structure thin film layers corresponding to symbols 1 to 7 in FIG. 2, respectively. 12 is AI, , , Ga0.7As
and a superlattice structure thin film layer consisting of GaAs, 13 is GaAs
14 is a single crystal thin film layer of A11. ．． 3Ga, ,,A
A single crystal thin film layer of s is shown.

第５図は、Ｓｉ上に形成するＧｅｘＳｉい、固溶体およ
びＳｎ、Ｇｅ１−、固溶体の組成と格子定数の関係およ
び実施例３と４に用いた超格子構造薄膜層の構成成分の
組成と格子定数との関係を示す。横軸はＸ、縦軸ｙは格
子定数をとする。１ないし５は基板からこの順序に形成
する超格子構造薄膜層を構成する２つの固溶体の組成と
格子不整合を示す。Figure 5 shows the relationship between the composition and lattice constant of the GexSi solid solution formed on Si, Sn, Ge1-, and the solid solution, and the composition and lattice constant of the constituent components of the superlattice structure thin film layer used in Examples 3 and 4. Indicates the relationship between The horizontal axis is X, and the vertical axis y is the lattice constant. 1 to 5 indicate the composition and lattice mismatch of two solid solutions constituting the superlattice structure thin film layer formed in this order from the substrate.

第６図、第７回においては、工ないし４は第３図および
第４図と同じものを示し、符号５ないし９は第５図の符
号工ないし５にそれぞれ対応する超格子、構造薄膜層を
示す。１０はＡｌ０１．Ｇａ、　、、ＡｓとＧｅＡｓか
らなる超格子構造薄膜層、１１はＧａＡｓの単結晶薄膜
層であり、１２はＡＮｏ、３Ｇａ０．、Ａｓのエピタキ
シー薄膜を示す。In FIGS. 6 and 7, numerals 5 to 4 indicate the same things as in FIGS. 3 and 4, and superlattices and structural thin film layers corresponding to numerals 5 to 5 in FIG. 5, respectively. shows. 10 is Al01. A superlattice structure thin film layer consisting of Ga, , , As and GeAs, 11 is a GaAs single crystal thin film layer, 12 is ANo, 3Ga0. , shows an epitaxial thin film of As.

実施例１ 一般のＳｉデバイスの作製に用いられるのと同様の鏡面
仕上げを行なったＳｉ（２１１）基板（第３図の符号１
）の表面の清浄化を、まずつぎのようなウェットプロセ
スで行なう。基板をトリクロールエチレン、アセトンと
純水とを用いて脱脂洗浄したのち、約１５０℃に加熱し
たＨ、０□／Ｈ２ＳＱ、（１／４）液に浸し表面の汚れ
を取り除く。つづいて純水で十分に洗浄したのち、　Ｈ
Ｆ／）１．０（１／１０）液に浸して表面の酸化膜を除
去する。このあと、大気にさらさない状態で純水を用い
て十分に洗浄し、加熱したＮＨ，ＯＨ／Ｈ，０□／Ｈ２
０（１／１／１０）液に浸し表面に極めてうすいシリコ
ンの酸化膜を形成して清浄化した表面を保護する。この
基板を分子線エピタキシー装置に充填し、８００℃に加
熱する。これにより表面に形成された酸化シリコン膜が
完全に除かれ、Ｓｉ基板の表面の清浄化が行なわれる。Example 1 A Si (211) substrate (reference numeral 1 in Fig.
) is first cleaned using the following wet process. After degreasing and cleaning the substrate using trichlorethylene, acetone, and pure water, it is immersed in H, 0□/H2SQ, (1/4) solution heated to about 150°C to remove surface stains. Next, after thoroughly washing with pure water,
F/) 1.0 (1/10) solution to remove the oxide film on the surface. After this, thoroughly wash with pure water without exposing it to the atmosphere, and heat the NH, OH/H, 0□/H2
0 (1/1/10) solution to form an extremely thin silicon oxide film on the surface to protect the cleaned surface. This substrate is packed into a molecular beam epitaxy apparatus and heated to 800°C. As a result, the silicon oxide film formed on the surface is completely removed, and the surface of the Si substrate is cleaned.

つぎにこの基板（第３図の符号１）の上に電子ビーム法
により作製したＳｉ分子ビームを用いてＳｉのバッファ
層（第３図の符号２）をエピタキシャル形成し、その上
にＳｉ分子ビームと抵抗加熱により作製したＧａ分子ビ
ームを用いて、第２図の符号１に対応する格子定数ａ　
＝５．５４５人の（ｉｓｌ、、　５　Ｓｉａ　−ｓ組成
の固溶体の約５０人の膜厚の単結晶薄膜（第３図の符号
３）と約５０人の膜厚のＳＬの単結晶薄膜（第３図の符
号４）の繰り返し多層構造すなわち超格子構造の薄膜層
（第３図の符号５）をエピタキシャル形成する。この超
格子構造を構成する２つの成分の格子不整合は２．１％
である。つぎにその上に第２図の符号２に対応する２つ
の組成の固溶体の超格子構造の薄膜層（第３図の符号６
）をエピタキシャル形成するにの場合、２つの成分間の
格子不整合は約１．７％であり、格子定数の小さい方の
値は、下側の超格子構造を構成する２つの成分の格子定
数の平均値番こ等しくなるようにとっである。このよう
にして、第２図の符号上なレル６に対応する超格子構造
薄膜の多層構造（第３図の符号５ないし１０）をエピタ
キシャル形成する。この場合、おのおの超格子構造を形
成する２つの成分の格子不整合は、第２図に示すように
、上の層はど小さくなっており、それらの２つの成分の
格子定数の平均値は、つぎにくる超格子構造を構成する
２つの成分の小さｂ）方の格子定数にほぼ等しくなり、
かつ上部に位置するほど大きくなっている。この上に第
２図の符号７に対応するＧｅａ　、９４５１０　＋Ｏｇ
固溶体とＳｎ６．ｏｚＧｅａ、ｓｅ固溶体の単結晶薄膜
層からなる超格子構造薄膜層（第３図の符号１１）を形
成し、それらの格子定数がＧｅの格子定数に一致するよ
うにする。この超格子構造の上に、約５０人のＡ１．　
、、Ｇａｌ、、、Ａｓの単結晶薄膜と約５０人のＧａＡ
ｓの単結晶薄膜層からなる超格子構造の薄膜層（第３図
の符号１２）をエピタキシャル形成し、その上にＧｅＡ
ｓの単結晶薄膜層（第３図の符号１３）をＧａとＡｓの
分子ビームを用い、エピタキシャル形成する。これによ
り、鏡面を示し、欠陥の少ないＧａＡｓ単結晶薄膜が形
成される。Next, a Si buffer layer (numeral 2 in Fig. 3) is epitaxially formed on this substrate (numeral 1 in Fig. 3) using a Si molecule beam produced by an electron beam method, and then the Si molecule beam Using a Ga molecular beam prepared by resistive heating, the lattice constant a corresponding to numeral 1 in FIG.
= 5.545 people (isl,, 5 Sia -s) A single crystal thin film (number 3 in Figure 3) with a thickness of about 50 people and a single crystal thin film of SL with a thickness of about 50 people ( A thin film layer (represented by reference numeral 5 in FIG. 3) having a repeating multilayer structure (reference numeral 4) in FIG. 3, that is, a superlattice structure is epitaxially formed.The lattice mismatch between the two components constituting this superlattice structure is 2.1%.
It is. Next, on top of that, a thin film layer with a superlattice structure of a solid solution of two compositions corresponding to the number 2 in FIG. 2 (the number 6 in FIG. 3) is applied.
), the lattice mismatch between the two components is approximately 1.7%, and the smaller value of the lattice constants is the lattice constant of the two components constituting the lower superlattice structure. The average value of is set to be equal to this number. In this way, a multilayer structure (numerals 5 to 10 in FIG. 3) of superlattice thin films corresponding to the reference layer 6 in FIG. 2 is epitaxially formed. In this case, the lattice mismatch between the two components forming each superlattice structure is smaller in the upper layer, as shown in Figure 2, and the average value of the lattice constants of these two components is It is approximately equal to the smaller lattice constant of the two components constituting the next superlattice structure,
And the higher it is located, the larger it is. On top of this, Gea, 94510 +Og, corresponding to number 7 in Fig. 2
Solid solution and Sn6. A superlattice structure thin film layer (reference numeral 11 in FIG. 3) consisting of a single crystal thin film layer of ozGea, se solid solution is formed so that its lattice constant matches that of Ge. On this superlattice structure, about 50 A1.
,,Gal,,,As single crystal thin film and about 50 GaA
A superlattice structure thin film layer (12 in FIG. 3) consisting of a single crystal thin film layer of s is epitaxially formed, and a GeA
A single crystal thin film layer (13 in FIG. 3) of s is epitaxially formed using molecular beams of Ga and As. As a result, a GaAs single crystal thin film exhibiting a mirror surface and having few defects is formed.

実施例２ 実施例１において、Ａ１．　、、Ｇａ、　、、ＡｓとＧ
ａＡｓからなる超格子構造薄膜層（第３図の符号１２）
の上に、Ａ１．　、、Ｇａ、　、、Ａｓ組成の単結晶薄
膜（第４図の符号１４）をＡＩ、ＧａとＡｓの分子ビー
ムを用いて、エピタキシャル形成する。これにより、同
様に、鏡面を示し、欠陥の少ないＧａＡｓ単結晶薄膜が
形成される。Example 2 In Example 1, A1. ,,Ga, ,,As and G
Superlattice structure thin film layer made of aAs (numeral 12 in Figure 3)
On top of A1. , , Ga, , , As, a single crystal thin film (reference numeral 14 in FIG. 4) is epitaxially formed using molecular beams of AI, Ga, and As. As a result, a GaAs single crystal thin film having a mirror surface and few defects is similarly formed.

実施例３ 実施例１と同じように、Ｓｉ（２１１）基板（第６図の
符号１）の表面の清浄化を行なったのち、Ｓｉのバッフ
ァ層（第６図の符号２）をエピタキシャル形成する。そ
の、上に、実施例１と同様に、ＳｉとＧｅ６　、Ｓ　５
１０−　ｓ固溶体からなる超格子構造薄膜層（第６図の
符号５）をエピタキシャル形成する。その上に第５図の
符号２ないし３に対応する組成を有する２つの組成の固
溶体の単結晶薄膜からなる超格子構造薄膜層をこの順序
に、第６図の符号６ないし８のようにエピタキシャル形
成する。この場合１つの超格子構造を構成する２つの固
溶体の格子定数の平均値が、そのつぎに位置する超格子
構造薄膜層を構成する２つの固溶体の小さい方の格子定
数に約０．２％の格子整合をするようにし、かつ上部に
位置するほど大きくなっている。この上に第５図の符号
５に対応するＧｅｌ＋＋９゜Ｓｉ、、、。とＳｎ、　、
。□にｅｏ、＊’＋固溶体の単結晶薄膜層からなる超格
子構造薄膜層（第６図）をエピタキシャル形成し、最上
層ではＧｅに十分に格子整合するようになっている。こ
の上に、ＡｌＡｓとＧａＡｓからなる超格子構造薄膜層
（第６図の符号１０）をエピタキシャル形成し、さらに
、ＧａＡｓの単結晶薄膜層（第６図の符号１１）をエピ
タキシャル形成する。これにより鏡面を有し、欠陥の少
ないＧａＡｓの単結晶薄膜が形成される。Example 3 As in Example 1, after cleaning the surface of the Si (211) substrate (number 1 in Figure 6), a Si buffer layer (number 2 in Figure 6) is epitaxially formed. . On top of that, as in Example 1, Si, Ge6, S5
A superlattice structure thin film layer (reference numeral 5 in FIG. 6) consisting of a 10-s solid solution is epitaxially formed. Thereon, a superlattice structure thin film layer consisting of a single crystal thin film of a solid solution having two compositions having compositions corresponding to numerals 2 to 3 in FIG. Form. In this case, the average value of the lattice constants of the two solid solutions constituting one superlattice structure is approximately 0.2% smaller than the smaller lattice constant of the two solid solutions constituting the next superlattice structure thin film layer. It is designed to match the lattice, and the higher the position, the larger the size. On top of this, Gel++9°Si corresponding to numeral 5 in FIG. and Sn, ,
. A superlattice structure thin film layer (FIG. 6) consisting of a single crystal thin film layer of eo, *'+ solid solution is epitaxially formed on □, and the uppermost layer is sufficiently lattice-matched to Ge. A superlattice structure thin film layer (10 in FIG. 6) made of AlAs and GaAs is epitaxially formed thereon, and a GaAs single crystal thin film layer (11 in FIG. 6) is further epitaxially formed. As a result, a GaAs single crystal thin film having a mirror surface and few defects is formed.

実施例４ 実施例３において＋’　Ａ（！ＡｓとＧａＡｓからなる
超格子構造薄膜層（第６図の符号１０）の上にＡ１．．
３Ｇａｏ、７Ａｓ組成の単結晶薄膜（第７図の１２）を
Ａｌ、Ｇａ、Ａｓの分子ビームを用いてエピタキシャル
形成する。これにより、鏡面をもち、欠陥の少ないＡ１
１０．、Ｇａ、　、□単結晶薄膜が形成される。Example 4 In Example 3, +'A (!A1...
A single crystal thin film (12 in FIG. 7) having a composition of 3 Gao and 7 As is epitaxially formed using molecular beams of Al, Ga, and As. This allows A1 to have a mirror surface and fewer defects.
10. , Ga, , □ A single crystal thin film is formed.

これらの実施例に用いているＳｉ（２１１）基板は、第
１図の符号１に示すように、結合手の１個が基板に平行
に存在していることから、その上に他のダイヤモンド構
造の単結晶薄膜層を形成し、その上にＧａＡｓを形成し
ても界面にチャージが生じないこと、および原子が結合
するサイトが、基板から上方にのびた１個の結合手にの
るサイト（第１図の符号２）と基板から上方にのびた２
個の結合手にのるサイト（第１図の符号３）の質的に異
なる２種類のサイトからなることから、その上にのる■
族と■広原子のサイ１〜・アロケーションが確定される
という特徴を有するので、本発明の目的にかなう基板で
ある。しかし、これらの目的をみたす基板は、これ以外
にも種々あり、第１図の状態から（１ｍ軸のまわりに回
転して作製した（２１１）方向が基板に対して傾斜した
結晶方位をもつ、たとえば（５４１）、　（４３１）、
　（３２１）などの基板を用いることができることは、
原理からみて明らかである。The Si(211) substrate used in these examples has one bond parallel to the substrate, as shown by reference numeral 1 in FIG. Even if a single-crystal thin film layer is formed and GaAs is formed on top of it, no charge will be generated at the interface, and the site where the atoms bond is the site on one bond extending upward from the substrate (the Number 2) in Figure 1 and 2 extending upward from the board
Since it consists of two qualitatively different types of sites (number 3 in Figure 1) that rest on individual bonds,
This substrate satisfies the purpose of the present invention because it has the characteristic that the size 1--allocation of the group and (1) wide atoms is determined. However, there are various other types of substrates that meet these objectives, such as substrates that have a crystal orientation in which the (211) direction is tilted with respect to the substrate, which is prepared by rotating around the 1 m axis from the state shown in Figure 1. For example (541), (431),
The fact that substrates such as (321) can be used is
This is obvious from the principle.

実施例工ないし３、および実施例４に示すように、超格
子構造の多層構造の形成において、１つの超格子構造を
形成する２つの固溶体（Ｓｉ　、　Ｇｅを含む）の格子
定数の平均値はそれに隣接する超格子構造を構成する２
つの成分の１つの格子定数に近くなるようにしている。As shown in Examples 3 to 3 and 4, in the formation of a multilayer superlattice structure, the average value of the lattice constants of two solid solutions (including Si and Ge) forming one superlattice structure is 2 constituting the superlattice structure adjacent to it
The lattice constant is made to be close to that of one of the two components.

これらの差は小さいほうがよいが、実施例３と４に示す
ように、エピタキシャル成長において一般に要請される
約０．２％以内の格子不整合なら特に問題はない。It is better that these differences be small, but as shown in Examples 3 and 4, there is no particular problem if the lattice mismatch is within about 0.2%, which is generally required in epitaxial growth.

実施例において、超格子構造薄膜層の多層構造の上にＡ
ｌ１０．、Ｇａ０．、Ａｓ−ＧａＡｓ系またはＡＪｉＡ
ｓ−ＧａＡｓ系の超格子構造の薄膜層をエピタキシャル
形成しているが、これは、この上に形成する■−■化合
物との格子整合をよくするとともに、下地の影響を緩和
するバッファ層の役目を果たしている。In the embodiment, A is applied on the multilayer structure of the superlattice structure thin film layer.
l10. , Ga0. , As-GaAs system or AJiA
A thin film layer with an s-GaAs superlattice structure is epitaxially formed, and this serves as a buffer layer to improve lattice matching with the ■-■ compound formed on top of it and to alleviate the effects of the underlying layer. is fulfilled.

また、ＡｉｄｘＧａニーｘＡＳ固溶体は全組成域でＧａ
Ａｓと格子整合するので、実施例で示した超格子構造薄
膜層は極めて良いバッファ層となる。実施例以外でもＩ
ｎｘＧａ１−ｘＰ固溶体、ＩｎｘＡｌ、ＧａＬ−、−、
Ｐ固溶体などの■−■化合物はＧａＡｓと格子整合する
ので、超格子構造薄膜のバッファ層の成分として用いる
ことができる。In addition, the AidxGaneexAS solid solution has Ga in the entire composition range.
Since it is lattice-matched to As, the superlattice structure thin film layer shown in the example becomes an extremely good buffer layer. I
nxGa1-xP solid solution, InxAl, GaL-, -,
A - - compound such as a P solid solution has a lattice match with GaAs, so it can be used as a component of a buffer layer of a superlattice structure thin film.

実施例において、■−■化合物としてＧａＡｓおよびＡ
ρ。、、Ｇａ、　、、Ａｓだけを用いているが、これ以
外でもＧａＡｓと十分に格子整合する■−■化合物、た
とえば全組成域のＡＮｘＧａニーＸＡｓ　ｌ特定の組成
域のＩｎＸＧａ、−ｘＰ、Ｉｎｘ１．Ｇａ１−ｘ−、Ｐ
固溶体なども用いることができる。In the examples, GaAs and A are used as the ■-■ compounds.
ρ. , , Ga, , , As are used, but there are other compounds that have a sufficient lattice match with GaAs, such as ANxGa, XAs, InXGa, -xP, Inx1, etc. in a specific composition range. Ga1-x-, P
Solid solutions can also be used.

なお、実施例においては、Ｓｉ基板の上にＳｉのバッフ
ァ層を形成しているが、これは基板表面の影響をできる
だけ避けるためにもうけたものであり。In the embodiment, a Si buffer layer is formed on the Si substrate, but this is provided in order to avoid the influence of the substrate surface as much as possible.

必ずしも必要でなく本発明必須の要件ではない。This is not necessarily necessary and is not an essential requirement of the present invention.

また、実施例においては、エピタキシャル法として分子
線エピタキシー法を用いているが、これ以外の方法、た
とえばＭＯＣＶＤなどの方法も用いることができる。Further, in the embodiment, molecular beam epitaxy is used as the epitaxial method, but other methods such as MOCVD may also be used.

（発明の効果） 本発明によれば、界面チャージが生じないようにするこ
と、サイト・アロケーションの確定により反位相構造が
生じないようにすること、ＧｅＡｓまたは、ＧａＡｓと
格子整合するｍ−ｖ化合物を形成する前にＧａＡｓと格
子整合するｍ−ｖ化合物の超格子構造の薄膜層を形成す
ることにより、下地の影響を緩和すること、およびＳｉ
とＧａＡｓまたはＧａＡｓと格子整合する■−■化合物
との間にある４、１％の格子不整合を、ＳｉとＧｅの固
溶体の超格子構造薄膜層の組成を段階的に変えた多層構
造の薄膜層とその上に形成した少量のＳｉを固溶したＳ
ｉ−Ｇｅ固溶体と少量のＳｎを固溶したＧｅ−、Ｓｎ固
溶体の超格子構造の薄膜層とをＳｉ層と■−■化合物層
の間に入れることで解消すること、などの課題解決によ
り、つぎのような効果がある。(Effects of the Invention) According to the present invention, interfacial charges are prevented from occurring, anti-phase structures are prevented from occurring by determining site allocation, and m-v compounds lattice-matched with GeAs or GaAs. By forming a thin film layer of a superlattice structure of an m-v compound that lattice-matches with GaAs before forming the Si
A multilayer structure thin film in which the composition of the superlattice structure thin film layer of a solid solution of Si and Ge is changed stepwise to compensate for the 4.1% lattice mismatch between S layer and a small amount of Si formed on it as a solid solution
The problem was solved by inserting a superlattice structure thin film layer of Ge-, Sn solid solution containing i-Ge solid solution and a small amount of Sn between the Si layer and the ■-■ compound layer. It has the following effects.

（１）　　ＳＬ基板上に高品質のＧａＡｓまたはＧａＡ
ｓと格子整合する■−■化合物が形成できることから。(1) High quality GaAs or GaA on SL substrate
This is because a ■-■ compound that is lattice-matched to s can be formed.

高価なＧａＡｓなどの■−■化合物を用いたデバイスを
安価に作製できる。Devices using expensive ■-■ compounds such as GaAs can be manufactured at low cost.

（２）　　さらに、Ｓｉ基板を用いていることの効果と
して、上記のデバイスとＳＬデバイスとを一体化、した
新らしいデバイスが作製できる。(2) Furthermore, as an effect of using a Si substrate, a new device that integrates the above device and an SL device can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はＳｉ　、　Ｇｅまたはそれらの固溶体のダイヤ
モンド構造図、第２図はＳｉ上に形成するＧｅｘＳｉ、
　−ｘ固溶体およびＳｎ、Ｇｅニー、固溶体の組成と格
子定数の関係図、第３図、第４図、第６図、第７図は本
発明によって形成される材料の断面図、第５図はＳｉ上
に形成するＧｅ、Ｓｉよ−８固溶体およびＳｎ、Ｇｅ□
−１固溶体の組成と格子定数の関係図である。 特許出願人　松下電器産業株式会社 第２図 第３図 第４図 第５図 第６図 第７図Figure 1 is a diagram of the diamond structure of Si, Ge or their solid solution, Figure 2 is a diagram of GexSi formed on Si,
Figures 3, 4, 6, and 7 are cross-sectional views of the material formed by the present invention, and Figure 5 is a diagram of the relationship between the composition and lattice constant of - Ge, Si-8 solid solution formed on Si and Sn, Ge□
FIG. 2 is a diagram showing the relationship between the composition and lattice constant of a -1 solid solution. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (12)

【特許請求の範囲】[Claims] （１）Ｓｉの結合サイトを構成する４個の結合手の１個
が基板に平行に存在した結晶方位を有する単結晶Ｓｉ基
板の上に、Ｇｅ、Ｓｉを含めて、Ｇｅ−Ｓｉ系の２つの
組成の固溶体の単結晶薄膜からなる超格子構造薄膜層の
多層構造を、超格子構造を構成する２つの固溶体の格子
定数の平均値が、上側に位置する超格子構造を構成する
２つの固溶体の小さい方の格子定数に近くなるようにし
、かつ上部方向に段階的に大きくなり、かつ、超格子構
造を構成する２つの固溶体の格子不整合が上方向に段階
的に小さくなるように形成し、その上にＧｅ−Ｓｉ系固
溶体と少量のＳｎを固溶したＳｎ−Ｇｅ系固溶体の単結
晶薄膜からなり、かつそれらの格子定数の平均値がＧｅ
の格子定数に十分に格子整合する超格子構造薄膜層を形
成し、該超格子構造薄膜層の上にＧｅＡｓと格子整合す
るIII−Ｖ化合物の間で構成される超格子構造薄膜層を
形成し、該超格子構造薄膜層の上にＧａＡｓと格子整合
するIII−Ｖ化合物の単結晶薄膜層を形成した構造を有
することを特徴とするIII−Ｖ化合物単結晶薄膜をそな
えたＳｉ基板。(1) Ge-Si based 2 A superlattice structure consisting of a single-crystal thin film of a solid solution with a composition of The lattice constant of the superlattice structure is made to be close to the smaller lattice constant of , consists of a single crystal thin film of a Sn-Ge solid solution on which a Ge-Si solid solution and a small amount of Sn are dissolved, and the average value of their lattice constants is Ge.
A superlattice structure thin film layer is formed that is sufficiently lattice-matched to the lattice constant of A Si substrate provided with a III-V compound single crystal thin film having a structure in which a single crystal thin film layer of a III-V compound lattice-matched to GaAs is formed on the superlattice structure thin film layer. （２）Ｓｉ（２１１）基板を用いることを特徴とする特
許請求の範囲第（１）項記載のIII−Ｖ化合物単結晶薄
膜をそなえたＳｉ基板。(2) A Si substrate provided with a III-V compound single crystal thin film according to claim (1), characterized in that a Si (211) substrate is used. （３）III−Ｖ化合物の間で形成される超格子構造薄膜
層として、ＧｅＡｓ、ＡｌＡｓおよびＡｌ＿ｘＧａ＿１
＿−＿ｘＡｓ固溶体の間で構成される超格子構造薄膜層
を用いることを特徴とする特許請求の範囲第（１）項記
載のIII−Ｖ化合物単結晶薄膜をそなえたＳｉ基板。(3) As a superlattice structure thin film layer formed between III-V compounds, GeAs, AlAs and Al_xGa_1
A Si substrate provided with a III-V compound single crystal thin film according to claim (1), characterized in that a superlattice structure thin film layer formed between ____xAs solid solutions is used. （４）Ｓｉ（２１１）基板を用いることを特徴とする特
許請求の範囲第（３）項記載のIII−Ｖ化合物単結晶薄
膜をそなえたＳｉ基板。(4) A Si substrate provided with a III-V compound single crystal thin film according to claim (3), characterized in that a Si (211) substrate is used. （５）III−Ｖ化合物の単結晶薄膜として、 Ａｌ＿ｘＧａ＿１＿−＿ｘＡｓ固溶体の単結晶薄膜層を
用いることを特徴とする特許請求の範囲第（３）項記載
のIII−Ｖ化合物単結晶薄膜をそなえたＳｉ基板。(5) A III-V compound single-crystal thin film according to claim (3), characterized in that a single-crystal thin film layer of an Al_xGa_1_-_xAs solid solution is used as the III-V compound single-crystal thin film. Si substrate. （６）Ｓｉ（２１１）基板を用いることを特徴とする特
許請求の範囲第（５）項記載のIII−Ｖ化合物単結晶薄
膜をそなえたＳｉ基板。(6) A Si substrate provided with a III-V compound single crystal thin film according to claim (5), characterized in that a Si (211) substrate is used. （７）Ｓｉの結合サイトを構成する４個の結合手の１個
が基板に平行に存在した結晶方位を有する単結晶Ｓｉ基
板の上に、Ｇｅ、Ｓｉを含めて、Ｇｅ−Ｓｉ系の２つの
組成の固溶体の単結晶薄膜からなる超格子構造薄膜層の
多層構造を、超格子構造を構成する２つの固溶体の格子
定数の平均値が、上側に位置する超格子構造を構成する
２つの固溶体の小さい方の格子定数に近くなるようにし
、かつ上部方向に段階的に大きくなり、かつ超格子構造
を構成する２つの固溶体の格子不整合が上方向に段階的
に小さくするようにエピタキシャル形成し、その上にＧ
ｅ−Ｓｉ系固溶体と少量のＳｎを固溶したＳｎ−Ｇｅ系
固溶体の単結晶薄膜層からなり、かつそれらの格子定数
の平均値がＧｅの格子定数に十分に格子整合する超格子
構造薄膜層をエピタキシャル形成し、該超格子構造薄膜
層の上にＧａＡｓと格子整合するIII−Ｖ化合物の間で
構成される超格子構造薄膜層をエピタキシャル形成し、
該超格子構造薄膜層の上にＧａＡｓと格子整合するIII
−Ｖ化合物の単結晶薄膜を形成することを特徴とするI
II−Ｖ化合物単結晶薄膜層をそなえたＳｉ基板の製造方
法。(7) Ge-Si based 2 A superlattice structure consisting of a single-crystal thin film of a solid solution with a composition of It is formed epitaxially so that the lattice constant of the superlattice is close to the smaller one of , on top of that
A superlattice structure thin film layer consisting of a single crystal thin film layer of an e-Si solid solution and a Sn-Ge solid solution containing a small amount of Sn, and whose average value of lattice constants is sufficiently lattice-matched to the lattice constant of Ge. epitaxially forming a superlattice structure thin film layer on the superlattice structure thin film layer, epitaxially forming a superlattice structure thin film layer composed of GaAs and a III-V compound lattice matched,
III which is lattice matched with GaAs on the superlattice structure thin film layer
-I characterized by forming a single crystal thin film of V compound
A method for manufacturing a Si substrate provided with a II-V compound single crystal thin film layer. （８）Ｓｉ（２１１）基板を用いることを特徴とする特
許請求の範囲第（７）項記載のIII−Ｖ化合物単結晶薄
膜をそなえたＳｉ基板の製造方法。(8) A method for manufacturing a Si substrate provided with a III-V compound single crystal thin film according to claim (7), characterized in that a Si (211) substrate is used. （９）III−Ｖ化合物の間で形成される超格子構造薄膜
層として、ＧａＡｓ、ＡｌＡｓおよびＡｌ＿ｘＧａ＿１
＿−＿ｘ固溶体の間で構成される超格子構造薄膜層を用
いることを特徴とする特許請求の範囲第（７）項記載の
III−Ｖ化合物単結晶薄膜をそなえたＳｉ基板の製造方
法。(9) As a superlattice structure thin film layer formed between III-V compounds, GaAs, AlAs and Al_xGa_1
Claim (7), characterized in that a superlattice structure thin film layer constituted between ____x solid solutions is used.
A method for manufacturing a Si substrate provided with a III-V compound single crystal thin film. （１０）Ｓｉ（２１１）基板を用いることを特徴とする
特許請求の範囲第（９）項記載のIII−Ｖ化合物単結晶
薄膜をそなえたＳｉ基板の製造方法。(10) A method for manufacturing a Si substrate provided with a III-V compound single crystal thin film according to claim (9), characterized in that a Si (211) substrate is used. （１１）III−Ｖ化合物の単結晶薄膜層として、ＧａＡ
ｓまたはＡｌ＿ｘＧａ＿１＿−＿ｘＡｓ固溶体の単結晶
薄膜を用いることを特徴とする特許請求の範囲第（９）
項記載のIII−Ｖ化合物単結晶薄膜をそなえたＳｉ基板
の製造方法。(11) As a single crystal thin film layer of III-V compound, GaA
Claim No. 9, characterized in that a single crystal thin film of s or Al_xGa_1_-_xAs solid solution is used.
A method for manufacturing a Si substrate provided with a III-V compound single crystal thin film as described in 1. （１２）Ｓｉ（２１１）基板を用いることを特徴とする
特許請求の範囲第（１１）項記載のIII−Ｖ化合物単結
晶薄膜をそなえたＳｉ基板の製造方法。(12) A method for manufacturing a Si substrate provided with a III-V compound single crystal thin film according to claim (11), characterized in that a Si (211) substrate is used.
JP22801084A 1984-10-31 1984-10-31 Si substrate provided with iii-v compound single crystal thin film and manufacture thereof Pending JPS61107721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22801084A JPS61107721A (en) 1984-10-31 1984-10-31 Si substrate provided with iii-v compound single crystal thin film and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22801084A JPS61107721A (en) 1984-10-31 1984-10-31 Si substrate provided with iii-v compound single crystal thin film and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61107721A true JPS61107721A (en) 1986-05-26

Family

ID=16869760

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JPS61107721A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897367A (en) * 1988-03-18 1990-01-30 Fujitsu Limited Process for growing gallium arsenide on silicon substrate
US5159413A (en) * 1990-04-20 1992-10-27 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
EP0681314A2 (en) * 1994-05-04 1995-11-08 Daimler-Benz Aktiengesellschaft Composite structure for electronic devices and method of making the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752126A (en) * 1980-09-16 1982-03-27 Oki Electric Ind Co Ltd Compound semiconductor device
JPS5753927A (en) * 1980-09-18 1982-03-31 Oki Electric Ind Co Ltd Compound semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752126A (en) * 1980-09-16 1982-03-27 Oki Electric Ind Co Ltd Compound semiconductor device
JPS5753927A (en) * 1980-09-18 1982-03-31 Oki Electric Ind Co Ltd Compound semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897367A (en) * 1988-03-18 1990-01-30 Fujitsu Limited Process for growing gallium arsenide on silicon substrate
US5159413A (en) * 1990-04-20 1992-10-27 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
US5164359A (en) * 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
US5356831A (en) * 1990-04-20 1994-10-18 Eaton Corporation Method of making a monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
EP0681314A2 (en) * 1994-05-04 1995-11-08 Daimler-Benz Aktiengesellschaft Composite structure for electronic devices and method of making the same
EP0681314A3 (en) * 1994-05-04 1996-09-04 Daimler Benz Ag Composite structure for electronic devices and method of making the same.

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