JPS61107233U - - Google Patents
Info
- Publication number
- JPS61107233U JPS61107233U JP19135184U JP19135184U JPS61107233U JP S61107233 U JPS61107233 U JP S61107233U JP 19135184 U JP19135184 U JP 19135184U JP 19135184 U JP19135184 U JP 19135184U JP S61107233 U JPS61107233 U JP S61107233U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- skip
- utility
- model registration
- waveform signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000750 progressive effect Effects 0.000 claims description 2
- 230000004069 differentiation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例の説明図、第２図は
同実施例の動作説明図、第３図は従来の順送りス
キツプ回路の説明図である。
１１……マトリツクス基板、１２……ダイオー
ドピン、１３……切替えスイツチ、又、２１……
入力スイツチ、２２……ワン・シヨツト・マルチ
回路（ＭＭ）、２３……カウンタ回路、２４……
デコーダ、２５……スキツプ・スイツチ回路、２
６……微分回路群、ＳＳ１〜ＳＳｎ……スキツプ
・スイツチ。
FIG. 1 is an explanatory diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the same embodiment, and FIG. 3 is an explanatory diagram of a conventional progressive skip circuit. 11... Matrix board, 12... Diode pin, 13... Changeover switch, and 21...
Input switch, 22... One shot multi circuit (MM), 23... Counter circuit, 24...
Decoder, 25...Skip switch circuit, 2
6...Differential circuit group, SS1 to SSn...Skip switch.
Claims (1)
し、このカウント値からデコード回路により入力
パルス数に対応したステツプ出力を発生する順送
りスキツプ回路において、デコーダの各ステツプ
出力端にそれぞれ接続され外部より切替え可能な
スキツプ・スイツチと、各スキツプ・スイツチに
接続されて微分波形信号を発生する微分回路と、
この微分回路の発生した微分波形信号をカウンタ
回路の入力側に加える手段を備えたことを特徴と
する順送りスキツプ回路。 (2) 微分回路の時定数が可変であることを特徴
とする実用新案登録請求の範囲第(1)項記載の順
送りスキツプ回路。[Claims for Utility Model Registration] (1) In a sequential skip circuit in which input pulses are counted by a counter circuit, and a step output corresponding to the number of input pulses is generated by a decoding circuit from this count value, a step output terminal of the decoder is provided. skip switches that are connected to each other and can be switched from the outside; a differentiation circuit that is connected to each skip switch and generates a differential waveform signal;
A forward skip circuit characterized by comprising means for applying a differential waveform signal generated by the differentiating circuit to an input side of a counter circuit. (2) The progressive skip circuit according to claim (1) of the utility model registration, characterized in that the time constant of the differentiating circuit is variable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19135184U JPS61107233U (en) | 1984-12-19 | 1984-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19135184U JPS61107233U (en) | 1984-12-19 | 1984-12-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107233U true JPS61107233U (en) | 1986-07-08 |
Family
ID=30748788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19135184U Pending JPS61107233U (en) | 1984-12-19 | 1984-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107233U (en) |
-
1984
- 1984-12-19 JP JP19135184U patent/JPS61107233U/ja active Pending
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