JPS61107018U - - Google Patents
Info
- Publication number
- JPS61107018U JPS61107018U JP19103284U JP19103284U JPS61107018U JP S61107018 U JPS61107018 U JP S61107018U JP 19103284 U JP19103284 U JP 19103284U JP 19103284 U JP19103284 U JP 19103284U JP S61107018 U JPS61107018 U JP S61107018U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- adjustment
- input
- resistor
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
第１図は本考案回路の一例を示す接続図、第２
図は従来回路の構成ブロツク図、第３図及び第４
図は第２図回路の動作を説明するための線図であ
る。
１…直流電源、２…伝送路、３…３端子レギユ
レータ、ｌ…伝送ライン、Ｒ１，Ｒ２…抵抗、Ｃ
１…コンデンサ。
Figure 1 is a connection diagram showing an example of the circuit of the present invention;
The figure shows the configuration block diagram of the conventional circuit, Figures 3 and 4.
This figure is a diagram for explaining the operation of the circuit of FIG. 2. 1...DC power supply, 2...Transmission line, 3...3-terminal regulator, l...Transmission line, R1 , R2 ...Resistance, C
1 ...Capacitor.
Claims (1)
子レギユレータを用いた電流リミツタ回路であつ
て、 前記３端子レギユレータ入力端子を入力直流電
源に接続するとともに、出力端子及び調整端子を
それぞれ抵抗Ｒ１及び抵抗Ｒ２を介して伝送器が
接続される伝送ラインに接続し、前記出力端子と
調整端子間にコンデンサを接続した電流リミツタ
回路。[Claims for Utility Model Registration] A current limiter circuit using a three-terminal regulator having an input terminal, an output terminal, and an adjustment terminal, wherein the input terminal of the three-terminal regulator is connected to an input DC power source, and an output terminal and an adjustment terminal. A current limiter circuit whose terminals are connected to a transmission line to which a transmitter is connected via a resistor R1 and a resistor R2, respectively, and a capacitor is connected between the output terminal and the adjustment terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19103284U JPH0530182Y2 (en) | 1984-12-17 | 1984-12-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19103284U JPH0530182Y2 (en) | 1984-12-17 | 1984-12-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61107018U true JPS61107018U (en) | 1986-07-07 |
| JPH0530182Y2 JPH0530182Y2 (en) | 1993-08-02 |
Family
ID=30748473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19103284U Expired - Lifetime JPH0530182Y2 (en) | 1984-12-17 | 1984-12-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0530182Y2 (en) |
-
1984
- 1984-12-17 JP JP19103284U patent/JPH0530182Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0530182Y2 (en) | 1993-08-02 |