JPS61105936A - Start-stop type data transmission system - Google Patents

Abstract

PURPOSE:To attain start-stop type two-way communication even without using an LSI especially by combining a shift register incorporated in a microcomputer and a control signal generating circuit as an external circuit. CONSTITUTION:When a transmission request signal DA is fed from a microcomputer 10 to a control signal generating circuit 20 at transmission, a start bit DB is generated from the circuit 20 and a clock pulse DC for the number of stages of the shift register (SR) 11, a data is read and transmitted from the SR11 by using the clock pulse DC. The circuit 20 generates the number of clock pulses for number of the stages of the SR11 based on the detection of the start bit DB at reception and fetches the reception data to the SR11. The enable state of amplifiers 31, 32 is controlled by using the control signal from the circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous bidirectional data transmission system.

[Conventional technology]

For example, video taken with a home video camera can be
When recording on a TR, in order to operate these two devices in synchronization, it is necessary to use the VTR as a master device and the video camera as a slave device and exchange data such as mode signals and control signals with each other. In this case, data may be communicated as digital signals by taking advantage of the fact that these devices are equipped with microcomputers these days. When considering the routing of transmission lines between devices, it is convenient to transmit digital data as serial data and to use asynchronous communication with a start bit/end bit.

By the way, when performing asynchronous data communication using a one-chip microcomputer commonly used in home VTRs, etc., one of the computer communication channel standards is used.
It is common to meet the R3-232C interface standard.

Conventionally, in order to satisfy the R5-232C standard, it has been common to use an expensive LSI for communication control in a one-chip microcomputer.

[Problem that the invention seeks to solve]

When communicating between consumer products such as home VTRs and video cameras, there are cost constraints, and it is not possible to use expensive LSIs to comply with the conventional R3-232G standard. There wasn't.

This invention is an improvement on this point.

[Means for solving problems]

The present invention provides a one-chip microcomputer αψ having a shift register (11) having a serial data input terminal, a serial data output terminal, and a clock terminal.
and a control signal generation circuit (20) for this shift register (11).

[Effect]

During transmission, when a transmission request signal is supplied to the control signal generation circuit (20), a start bit is generated from the control signal generation circuit (20) and the shift register (11)
A clock pulse corresponding to the number of stages is generated, and data is read out from the shift register (11) using this clock pulse and transmitted. At the time of reception, data is read out from the shift register (11) based on the detection of the start bit by the control signal generation circuit (20). 11
) is generated, and the received data is taken into the shift register (11) using the clock pulses.

〔Example〕

FIG. 1 shows an example of the present invention, in which a consumer 1-chip microcomputer and an R5-232G are connected, and is an example of full duplex communication.

αΦ is a 1-chip microcomputer, (11) is its built-in 8-bit shift register, and this shift register (11) has a serial data input terminal SI, a serial data output terminal SO, and a clock terminal CK. ing.

Further, (20) is a control signal generation circuit that generates a control signal for the shift register (11), and a crystal oscillator (21).
) from the control clock signal (one period is, for example, 104 μs)
ec), the circuit operates as described below. Note that this circuit (20) can also be realized by a microcomputer.

Further, (31) and (32) are amplifiers whose enable states are controlled by control signals, which will be described later, from the control signal generation circuit (20), respectively, and (33) and (32), respectively.
34) is a voltage conversion circuit.

The microcomputer allO1 control signal generation circuit (20) and amplifier (31) (32) shown in FIG.
) etc. are provided on both the VTR side and the camera side, for example, when communicating between a VTR and a camera, but since their operations are exactly the same, they are only needed on one side. I will explain about this. It should be noted that it is not necessary to provide it in both devices as long as the other device has a configuration that allows asynchronous communication.

(40) and (41) are communication lines connecting the own devices, and communication is performed at 9600 baud (1 data is 104 #sec).

First, the transmission operation of this device will be explained.

A transmission request signal DA (FIG. 2A) is generated from the microcomputer αω, and is supplied to the control signal generation circuit (20) through a terminal (20^).

This transmission request signal DA is normally "1" and falls to "0" when requesting transmission. Then, in the circuit (20), the start bit DB (Fig. 2B) which becomes 1-0 for a specified length of 104 μsec is obtained in the start bit generation circuit (22) from the rising edge of the signal DA. , which is supplied to the addition AND gate (35) through the terminal (20B) and placed on the external transmission line (40).

Further, the transmission request signal DA is delayed by one clock period from the oscillator (21) in the delay circuit (23), and this delayed signal is passed through the OR game 1-(24) to the clock generation circuit (
Based on this, eight clock pulses DC (Fig. 2C) with a clock period of 104 μSec are obtained from this clock generation circuit (25), and these are sent to the shift register (11) through the terminal (20G). is supplied to the clock terminal CK of the clock terminal CK.

Further, the output signal of the delay circuit (23) is supplied to the area signal generation circuit (26), which generates a period of 8 bits "1".
An area signal DD (FIG. 2D) is obtained and is supplied to AND gates (27R) and (27T).

Furthermore, the transmission request signal DA through the terminal (20A) is supplied to the transmission/reception discrimination circuit (28), and during this transmission, one output GR is "0" and the other output GT is r
It is assumed to be lJ. And the output GR is an AND gate (27
The output GT is supplied to the AND gate (27T), so the gate is turned off, and the output GT is supplied to the AND gate (27T), so the gate is turned off. Therefore, during transmission, the output of the AND gate (27T) becomes rlJ during the period when the area signal DD is "1", and this is supplied to the amplifier (31) through the terminal (200).
is enabled.

Then, in the microcomputer αψ, the transmission request signal D
When outputting A, the transmission data I)E (Fig. 2E) is set in advance in the shift register (11), so when the transmission request signal DA is generated from the above, first the control signal generation circuit ( Starting from 2o) DB occurs, followed by 8 (+1i+ clock pulse DC).
The data DE is read out from the shift register (11), and this is sent to the AND gate (
35) and is added to the start bit DB, and this added transmission signal DF (FIG. 2 F) is led out to the transmission terminal (30T) through the voltage conversion circuit (33) and is put on the communication line (40). It will be done.

Next, the reception operation will be explained.

The signal DC transmitted through the communication line (41) is
As shown in Figure G, a start bit is provided at the beginning, followed by 8-bit serial data. This signal DG is passed through the receiving terminal (30R) to the voltage conversion circuit (30R).
4) to the amplifier (32), and also to the reception start bit detection circuit (29) through the terminal (20g) of the control number generation circuit (2o). When the start bit is detected in this detection circuit (29), a signal DH (H in FIG. 2) is obtained as its detection output. This signal DH is supplied to the transmission/reception mode discriminating circuit (28) and is also supplied to the microcomputer through the terminal (20F) as a reception request signal. In response to this, the microcomputer αω changes the shift register (1
1) is enabled and this shift register (11
) until 8 bits of data are stored.

The signal DH is also supplied to the delay circuit (23') and
The clock pulse period is delayed by 104 μsec, and the delayed signal is sent to the clock pulse generation circuit (
25) and an area generation circuit (26). Then, from the area generation circuit (26), a period of 8 bits "
1'' (FIG. 2 I) is obtained. At this time, the transmission/reception mode discrimination circuit (28) discriminates the signal DH so that one output GR becomes "1" and the other output GT becomes rOJ, so the signal DD is extracted through the AND gate (27R). , this is the terminal (20G)
is supplied to the amplifier (32) through the amplifier (32).
It becomes enabled during the 8-bit period in which it becomes "1".

Therefore, the data DC is supplied to the input terminal SI of the shift register (11). At this time, eight clock pulses DC (Fig. 2 J
) is obtained, and data DC is taken into the shift register (11) by this clock pulse (K in FIG. 2). Although not shown, when all 8 bits are taken in, the data is taken into the RAM of the microcomputer aω, decoded, and predetermined control is performed on the equipment incorporating the microcomputer αω.

FIG. 3 shows another example of this invention, in which the second example is transmission.

This is a case where reception is performed using one common communication line (43). In this example, one device that is connected to ζF via the communication line is the master device, the other device 2:( is the slave device, and the start bit is generated only from the master device.And, Transmission from the master device to the slave device and reception of transmission data from the slave device by the master device are done in a time-sharing manner.For example, as shown in FIG. This process is repeated with the reception period P2 of the data from the device in the master device as one block, and the start bits X1 and X2 are set to the period PL.
, generated only from the master device before P2. Then, transmission is performed based on the start bit 'Xx as in the past, and reception is performed by transmitting start bit X2 to the slave side, causing data to be transmitted from the slave side based on this, and transmitting this transmission data to start bit X2. The master device receives the information based on the received information. In this case, an end bit period T1 between periods P1 and P2;
The period T2 between blocks is made sufficiently distinguishable to prevent malfunctions.

In this example, the reception start bit detection circuit (29) and its related circuits in the example of FIG. 1 are not provided.

In this example, start bits X1 and X2 are generated at a predetermined repetition period, and a communication start signal DK (FIG. 5A) for performing communication is obtained from the microcomputer a, and this is sent to the terminal ( 20^) to the star bit generation circuit (22), from which start bits X1 and X2 are generated (FIG. 5B). Following these start bits X1 and X2, eight clock pulses DC (
5C) is obtained, which is supplied to the clock terminal of the shift register (11).

At the same time, a signal DD (FIG. 5D) is obtained from the area generation circuit (26), each having an 8-bit period rlJ in which the clock pulse DC is obtained.

On the other hand, of the communication start signal DK, a pulse Y1 obtained before the period Pl and a pulse Y2 obtained before the period P2
From this, the output OR, GT of the transmission/reception discrimination circuit (280) becomes one output GR (Fig. 5E) during the period including period P1.
is "0", the other output GT (F in the same figure) is "1", and the period P
In the period including 2, the output GR is "1" and the output GT is rOJ.
becomes.

Therefore, during period P1, the switch circuit (36) is turned on, and the data that has been sent to the shift register (11) is transmitted through the adder circuit (38) with start bits X1 and X2 added thereto. Also, during period P2, the switch circuit (37) is turned on, and the data sent from the slave device is transferred to the shift register (11) via the switch circuit (37) and taken in (Fig. 5G).
reference).

In addition, as shown in FIG. 6, the control signal generation circuit (20)
and amplifiers (31) to (35) or switch circuits (36)
) The serial input terminals, serial output terminals, and clock terminals of each shift register of a plurality of microcomputers (51) to (54) are commonly connected to the circuit (200) including (37), and any one of the microcomputers (51) to (54) is The computer (51) is the main one, and the main microcomputer (51) supplies chip select signals CS1*C52, C33 to each microcomputer to select which microcomputer is to be enabled for communication. By doing so, communication of data from a plurality of electronic devices incorporating each of these microcomputers (51) to (54) through the communication line (300) can be commonly controlled.

Furthermore, in the above example, it is possible to use the clock CL of the microcomputer α as the shift clock pulse for the shift register (11), but this clock CL is used for the timer and as a clock for processing as quickly as possible.・Tsuku, 9600 baud, 48
Even set the clock to a baud rate like 00 paws. In this regard, if the shift clock pulse is formed in a separate circuit (20) from the microcomputer α0 as in the above example, a clock that matches the baud rate for communication can be easily obtained. Furthermore, there is no need to change the software on the microcomputer.

〔Effect of the invention〕

According to this invention, by combining a shift register built into a microcomputer and a control signal generation circuit as an external circuit, it is possible to perform step-synchronous synchronization in both directions without using a conventional LSI for R5-232C. Communication is mouth J
become capable. The control signal generation circuit can be expected to be manufactured at a lower cost than conventional LSIs, and is very useful for communication between home VTRs and video cameras.

Further, since communication compatible with the R5-232G standard is possible, it becomes easy to connect electronic equipment equipped with this invention to other microcomputers.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of this invention, FIG. 2 is a diagram for explaining it, FIG. 3 is a block diagram of another example of this invention, and FIGS. 4 and 5 are for explaining it. 6 are block diagrams showing an example of application of the present invention. Alpha is a one-chip microcomputer, (11) is its built-in shift register, and (20) is a control signal generation circuit. Figure 5 zoU

Claims (1)

[Claims] It has a one-chip microcomputer having a shift register equipped with a serial data input terminal, a serial data output terminal, and a clock terminal, and a control signal generation circuit for the shift register, and when transmitting, the control signal generation circuit When a transmission request signal is supplied, this control signal generation circuit generates a start bit and generates clock pulses as many as the number of stages of the shift register, and uses these clock pulses to read data from the shift register and transmit it. During reception, the control signal generation circuit generates clock pulses equal to the number of stages based on the detection of a start bit, and the received data is loaded into the shift register using the clock pulses. .