JPS61105914A - Mixer circuit - Google Patents

Mixer circuit

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Publication number
JPS61105914A
JPS61105914A JP22854184A JP22854184A JPS61105914A JP S61105914 A JPS61105914 A JP S61105914A JP 22854184 A JP22854184 A JP 22854184A JP 22854184 A JP22854184 A JP 22854184A JP S61105914 A JPS61105914 A JP S61105914A
Authority
JP
Japan
Prior art keywords
gaas
fet
drain
output
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22854184A
Other languages
Japanese (ja)
Other versions
JPH0374965B2 (en
Inventor
Noboru Kusama
草間 昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22854184A priority Critical patent/JPS61105914A/en
Publication of JPS61105914A publication Critical patent/JPS61105914A/en
Publication of JPH0374965B2 publication Critical patent/JPH0374965B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To suppress sufficiently any of a couple of input signals at an output terminal to a small value by connecting a double pair differential amplifier circuit to the output terminal of each amplifie circuit so as to cancel the leakage component in order to obtain a large separation between a couple of input signal terminals. CONSTITUTION:GaAs-FETs116-119 forming the double pair differential amplifier circuits give an output of a GaAs-FET110 to a load resistor 120 or 121 according to the polarity of a control voltage given to a gate to switch the two modes of the output of a GaAs-FET111. The 2nd frequency signal fed to an input terminal 103 is amplified by the GaAs-FET113, 114 forming the differential amplifier circuit to apply switch control to the output of the GaAs- FET116-119 forming the double pair differential amplifier circuits. The signal fed to the 1st and 2nd signal input terminals 102, 103 is fed to the GaAs-FET 116-119 forming the double pair differential circuits while being balanced, then the crosstalk to output terminals 106, 107 is less.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、マイクロ波帯信号周波、数を変換するミクサ
回路の回路構成に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit configuration of a mixer circuit that converts microwave band signal frequencies and numbers.

(従来の技術) 低い周波数帯ではバイポーラトランジスタを使用して差
動増幅回路が構成されるが、その場合にはペース・工は
ツタ間で電圧対電流特性の非直線性を改善するため、第
3図に示すようにバイポーラトランジスタ351.δ5
2の工ばツタにそれぞれ直列抵抗35ろ、354を追加
しなければならない。これらの抵抗353.354によ
シ雑音指数が劣化することはバイポーラトランジスタが
マイクロ波帯でG a A s −F E Tに比べて
雑音指数が高いことと相まって、実用的なマイクロ波帯
ミクサをバイポーラトランジスタで構成する防げとなっ
ていた。
(Prior art) In low frequency bands, differential amplifier circuits are constructed using bipolar transistors, but in this case, the pace amplifier is used to improve the nonlinearity of the voltage vs. current characteristics between the vines. As shown in FIG. 3, a bipolar transistor 351. δ5
It is necessary to add series resistors 35 and 354 to the second step, respectively. The deterioration of the noise figure due to these resistors 353 and 354, combined with the fact that the bipolar transistor has a higher noise figure than the GaAs-FET in the microwave band, makes it difficult to create a practical microwave band mixer. It was made up of bipolar transistors.

一方、GaAs−FETはマイクロ波帯で高利得が得ら
れるデバイスとして、以前から増幅器やミクサに使用さ
れている。Q a A s −F E Tを使用したミ
クサの一例は第4図に示すように、単一のGaAs’−
FETを使用し、歪特性を利用して一対の入力信号の和
または差の周波数の信号を生成していた。第4図におい
て、401はドレーン電源供給端子、402,403は
それぞれ信号入力端子、406は信号出力端子、450
はGaA1−FET、431は負荷抵抗器である。
On the other hand, GaAs-FETs have long been used in amplifiers and mixers as devices that can obtain high gain in the microwave band. An example of a mixer using QaAs-FET is shown in FIG.
FETs were used to generate a signal with the frequency of the sum or difference of a pair of input signals by utilizing distortion characteristics. In FIG. 4, 401 is a drain power supply terminal, 402 and 403 are signal input terminals, 406 is a signal output terminal, and 450
is a GaA1-FET, and 431 is a load resistor.

(発明が解決しようとする問題点) 上に説明した構成においては、単一のデバイスに8つの
異なる周波数が存在するため、上記一対の入力信号間の
分離が不足しているという欠点と、出力端子に入力信号
の一部が出力さhてしまうという欠点があった。
(Problems to be Solved by the Invention) The configuration described above suffers from the drawbacks of lack of isolation between the pair of input signals and the lack of separation between the pair of input signals due to the presence of eight different frequencies in a single device. There was a drawback that part of the input signal was output to the terminal.

また、従来方式のミクサでは局部発振信号の出力端子へ
の涌れを補正するため補正回路を付加すると、局部発振
信号に中間周波数信号を混合して生成した送信出力が局
部発振側端子にも漏れるので、この信号が補正回路を通
って出力端子へ送出される。この漏れ出力と正規の信号
の出力とでは遅延時間が大幅に異なるため、伝送特性に
はエコー歪が生じてしまうという欠点がめった。
In addition, in conventional mixers, when a correction circuit is added to correct the local oscillation signal flowing to the output terminal, the transmission output generated by mixing the local oscillation signal with the intermediate frequency signal also leaks to the local oscillation side terminal. Therefore, this signal passes through the correction circuit and is sent to the output terminal. Since the delay time between this leakage output and the output of the normal signal is significantly different, echo distortion often occurs in the transmission characteristics.

本発明の目的は、一対の入力信号端子間に大きな分離度
を得るため、それぞれの増幅回路の出力端に双対の差動
増幅回路を上記漏れ成分を相互に打消すように接続する
ことによって上記欠点を除去し、出力端子には上記一対
の入力信号のいずれもが十分に小さく抑圧できるように
構成したQaA s −F E Tによるばフサ回路を
提供することにおる。
An object of the present invention is to connect a pair of differential amplifier circuits to the output terminals of each amplifier circuit so as to cancel out the leakage components. The object of the present invention is to provide a filter circuit using QaA s-FET, which eliminates the drawbacks and is configured such that both of the above-mentioned pair of input signals can be suppressed to a sufficiently low level at the output terminal.

(問題点を解決するための手段) 本発明によるミクサ回路はQ a A s −N E 
Tによるもので、第1〜第1OのGaAs−FETと第
1および112の抵抗器とから成るものでおる。
(Means for solving the problem) The mixer circuit according to the present invention is Q a A s -N E
It consists of first to first Oth GaAs-FETs and first and 112th resistors.

第1および第2のGaAs−FETはソースを共通接続
し、ソース共通接続点に第1の抵抗器を接続したもので
ある。
The sources of the first and second GaAs-FETs are commonly connected, and the first resistor is connected to the common source connection point.

第8のGaAs−NETは第2のQ a A s −F
ETのゲートにゲートを接続し、ソースを第1および第
2のQ a A s −N E Tと第1の抵抗器との
ソース共通接続点に接続したものである。
The eighth GaAs-NET is the second Q a As -F
The gate is connected to the gate of the ET, and the source is connected to a common source connection point between the first and second QAs-NET and the first resistor.

#1の抵抗器は一端を上記ソース共通接地点に接続し、
他端を接地電位点に接続したものである。
Connect one end of resistor #1 to the source common ground point,
The other end is connected to the ground potential point.

第4および第5のG a A s −F E Tは、第
1のG a A s −F E Tのドレーンにソー2
を接続したものである。
The fourth and fifth GaAs-FETs are connected to the drain of the first GaAs-FET.
is connected.

第6のGaAs−FETは、第2(7’)GaAs −
FETのドレーンにソニスを接続し、第5のGaAs−
FETのゲートにゲートを接続し、第4のG a A 
s −F E Tのドレーンにドレーンを接続したもの
である。
The sixth GaAs-FET is the second (7') GaAs-FET.
Connect the Sonis to the drain of the FET and connect the fifth GaAs-
Connect the gate to the gate of the FET, and connect the fourth G a A
The drain is connected to the drain of s-FET.

第7のQ a A s −F E Tは、第2のGaA
s−FETのドレーンにソースを接続し、第4のQaA
 s−F ETのゲートにゲートを接続し、第5のQ 
a A s −F E Tのドレーンにドレーンを接続
したものである。
The seventh QaAs-FET is the second GaA
Connect the source to the drain of the s-FET and connect the fourth QaA
Connect the gate to the gate of s-FET and connect the fifth Q
The drain is connected to the drain of aAs-FET.

第8のGaAs−FETは第2の抵抗器にソースを接続
し、第5および第6のG a A s −F ETのゲ
ートにドレーンを接続したものでおる。
The eighth GaAs-FET has its source connected to the second resistor, and its drain connected to the gates of the fifth and sixth GaAs-FETs.

第9のGaAs−FETは、第8のQ&Al1−FET
のソースおよび第2の抵抗器にソースを接続し、第4お
よび第7のGaAs−FETのゲートにドレーンを接続
したものでめる。
The ninth GaAs-FET is the eighth Q & Al1-FET
The source is connected to the source and the second resistor, and the drain is connected to the gates of the fourth and seventh GaAs-FETs.

第2の抵抗器は、第8および第9のGaAs−FETの
ソースに接地電位点との間に接続したものである。
The second resistor is connected between the sources of the eighth and ninth GaAs-FETs and the ground potential point.

第10のGaAs −F E Tは、第8および第9の
Q a A s −F g Tのゲートにゲートを接続
し、第8および第9のG a A s −F E Tの
ソースおよび第2の抵抗器の共通接続点にソースを接続
したものである。
The tenth GaAs-FET has its gate connected to the gates of the eighth and ninth QaAs-FgTs, and connects the sources of the eighth and ninth GaAs-FETs and the gates of the eighth and ninth QaAs-FgTs. The source is connected to the common connection point of the two resistors.

上記構成に2いて、本発明はw、1および第8のGaA
s−FETのゲート共通接続点から第1の周波数の高周
波信号を加え、第9および第10のGaAs−FETの
ゲート共通接続点から第2の周波数の高周波信号を加え
、第4および第6のGa A s −N E Tのドレ
ーン共通接続点、または第5および第7のQ a A 
s −N E Tのドレーン共通接続点から81および
第2の周波数の高周波信号の和または差の周波数を有す
る第3の高周波信号を取出すことができるように構成し
たものである。
In the above configuration 2, the present invention provides w, 1 and 8th GaA
A high frequency signal of a first frequency is applied from the gate common connection point of the s-FET, a high frequency signal of the second frequency is added from the gate common connection point of the ninth and tenth GaAs-FETs, and a high frequency signal of the second frequency is applied from the gate common connection point of the ninth and tenth GaAs-FETs. Ga A s - N ET drain common connection point or fifth and seventh Q a A
The configuration is such that a third high frequency signal having a frequency that is the sum or difference of the high frequency signals of 81 and the second frequency can be taken out from the drain common connection point of s-NET.

(実施例) 次に、本発明について図面を参照して詳細に説明する。(Example) Next, the present invention will be explained in detail with reference to the drawings.

第】図は、本発明によるiフサ回路の一実施例を示す回
路図である。第1図において、101は電源用端子、1
02は第1の周波数信号の入力端子、10るは第2の周
波数信号の入力端子、106゜107はそれぞれ信号の
出力端子、104,105はそれぞれバイアス用端子、
110〜119はそれぞれGaAs−FET、120〜
126はそれぞれ抵抗器である。一対のGaAs−FE
T110.111は第1の周波数信号用の差動増幅回路
であって、GaAs−FET1tOのドレーン側に逆相
の出力が得られ、GaAs−FET111のドレーン側
に正相の出力が得られる。双対の差動増幅回路を形成す
るG a A s −F ET116〜119はゲート
に加えられる制am圧の極性に従ってGaAs−FET
110の出力を負荷抵抗器120へ接続してGaAs−
FET111の出力を負荷抵抗器121へ接続するか、
あるいはGaAs−FET110の出力を負荷抵抗器1
21へ接続してGaAs−FET111の出力を負荷抵
抗器120へ接続するかの2つのモードの切換え動作を
行うものである。入力端子106に加えられた第2の周
波数の信号は差動増幅回路を形成するGaAs−FET
11ろ、114で増幅され、双対差動増幅回路を形成す
るQaA8−FET116〜119の出力の切換え制御
を行うものである。@1および第2の信号入力端子10
2.106に加えられた信号は共に平衡して双対差動回
路を形成するGaAs−FET 116〜119に加え
られるため、出力端子106゜107への漏れが少ない
。一般に抵抗器125の値が小さいとGaAs−FET
 110 、111による差動増幅回路ではGaAs−
FET111のドレーンに現れる正相の出力がG a 
A s −F E T110のドレーンに現れる逆相の
出力に比べて低くなりやすい。このような場合には、双
対差動増幅回路116〜119に加える信号の平衡性を
劣化させ、出力端子106,107への漏れの発生原因
にもなる。
FIG. 1 is a circuit diagram showing an embodiment of an i-fusa circuit according to the present invention. In FIG. 1, 101 is a power supply terminal;
02 is an input terminal for the first frequency signal, 10 is an input terminal for the second frequency signal, 106 and 107 are signal output terminals, 104 and 105 are bias terminals,
110 to 119 are GaAs-FETs, 120 to 119 are respectively GaAs-FETs,
126 are resistors, respectively. A pair of GaAs-FE
T110 and T111 are differential amplification circuits for the first frequency signal, and an output in reverse phase is obtained on the drain side of the GaAs-FET1tO, and an output in positive phase is obtained on the drain side of the GaAs-FET111. The GaAs-FETs 116 to 119 forming the dual differential amplifier circuit are GaAs-FETs according to the polarity of the suppressing am pressure applied to the gates.
Connect the output of 110 to the load resistor 120 to connect the GaAs-
Connect the output of FET 111 to load resistor 121, or
Alternatively, connect the output of GaAs-FET 110 to load resistor 1
21 and the output of the GaAs-FET 111 is connected to the load resistor 120. The second frequency signal applied to the input terminal 106 is applied to a GaAs-FET forming a differential amplifier circuit.
11 and 114 to control switching of the outputs of QaA8-FETs 116 to 119 forming a dual differential amplifier circuit. @1 and second signal input terminal 10
Since the signals applied to 2.106 are balanced together and applied to the GaAs-FETs 116 to 119 forming a dual differential circuit, there is little leakage to the output terminals 106 and 107. Generally, if the value of resistor 125 is small, GaAs-FET
In the differential amplifier circuit based on 110 and 111, GaAs-
The positive phase output appearing at the drain of FET111 is Ga
It tends to be lower than the reverse phase output appearing at the drain of A s -F ET110. In such a case, the balance of the signals applied to the dual differential amplifier circuits 116 to 119 will be degraded, and this will also cause leakage to the output terminals 106 and 107.

本発明ではGaAs−FET112′t−追加し、入力
端子102に加えられた第1の周波数の正相側の信号を
抵抗器125によって補正し、GaAs−FET111
のドレーンへ出力しているためGaAs−FETを使用
した差動増幅回路で生じやすい正相側のレベル低下にも
とづく平衡性の劣化を防止している。第2の周波数を増
幅する差動増幅回路を形成するGaAs−FETI 1
3゜114に対してもGaAs−FET115を追加し
て平衡性を改善している。Ga A s −F E T
116〜115から成る差動増幅回路は不平衡信号を平
衡信号に改善する作用のみならず、第2の周波数の信号
を増幅し、双対差動増幅回路を形成するGaAs−FE
T 116〜119に存在する信号が入力端子106へ
漏れ出すことがないように防止する働きもめる。入力端
子102からみた場合でも入力端子10るからみたほど
ではないがGaAs−FET110〜112から成る差
動増幅回路がバッファ作用を有するため、双対差動増幅
回路を形成するGaAs−FET 116〜119に存
在する信号が漏れ出すことがないように防止する働きが
ある。
In the present invention, a GaAs-FET 112't- is added, and the signal on the positive phase side of the first frequency applied to the input terminal 102 is corrected by a resistor 125.
Since the signal is output to the drain of the signal, it is possible to prevent deterioration of balance due to a drop in the level on the positive phase side, which tends to occur in differential amplifier circuits using GaAs-FETs. GaAs-FETI 1 forming a differential amplifier circuit that amplifies the second frequency
A GaAs-FET 115 is also added to the 3°114 to improve balance. GaAs-FET
The differential amplifier circuit consisting of 116 to 115 not only improves an unbalanced signal to a balanced signal, but also amplifies the second frequency signal and forms a dual differential amplifier circuit.
It also works to prevent the signals present at T 116 to 119 from leaking to the input terminal 106. Even when viewed from the input terminal 102, the differential amplifier circuit consisting of GaAs-FETs 110 to 112 has a buffer effect, although it is not as strong as when viewed from the input terminal 10. It works to prevent existing signals from leaking out.

第1図に示すように、入力端子103より局部発振信号
を入力し、入力端子102よシ高周波信号を加えれば高
周波信号の混変調特性が改善される。第1図においては
、抵抗器124を挿入し、入力端子10ろに加えるべき
局部発振信号レベルを多少高めることによってGaAs
−FET116〜119の切換え動作時の波形を矩形に
することができ、高周波信号の混変調特性をさらに一層
改善することができる。また、本発明によるミクサ回路
を入力端子103から局部発振信号を入力し、入力端子
102から中間周波数信号を入力し、出力端子106ま
たは出力端子107から出力を得るものとする。出力端
子106,107と入力端子10ろとの間に位相とレベ
ルとが可変な補償回路を追加することによって、伝送信
号の混変調特性に優れ、出力端子106,107に局部
発振信号の漏れや熱雑音が少ない送信ミクサが構成され
る。
As shown in FIG. 1, by inputting a local oscillation signal through input terminal 103 and adding a high frequency signal through input terminal 102, the cross-modulation characteristics of the high frequency signal can be improved. In FIG. 1, by inserting a resistor 124 and increasing the local oscillation signal level to be applied to the input terminal 10,
- The waveform during the switching operation of the FETs 116 to 119 can be made rectangular, and the cross modulation characteristics of high frequency signals can be further improved. Further, it is assumed that the mixer circuit according to the present invention receives a local oscillation signal from an input terminal 103, receives an intermediate frequency signal from an input terminal 102, and obtains an output from an output terminal 106 or an output terminal 107. By adding a compensation circuit with variable phase and level between the output terminals 106, 107 and the input terminal 10, the cross-modulation characteristics of the transmission signal are excellent, and the leakage of local oscillation signals to the output terminals 106, 107 is prevented. A transmission mixer with low thermal noise is constructed.

第2図は、斯かるばフサ回路の一応用例による周波数変
換装置を示すブロック図である。第2図において、24
2は中間周波増幅回路、241は中間周波信号の入力端
子、243は局部発振回路、247は111図に示すミ
クサ回路、245゜246はそれぞれ位相とレベルとを
可変できる補正回路であり、245は半固定インダクタ
ンス、246は半固定抵抗器である。伝送特性の混変調
特性を改善するためには中間周波信号のレベルを十分に
絞り、直線性のよい小信号レベル範囲で使用する。斯か
る場合には相対的に局部発振レベルが高くなり、ミクサ
回路の平衡特性が優れていても出力端子における局部発
振信号の漏れの量がめだつようになる。これを補正する
ためインダクタ45と抵抗器46とから成る補正回路を
設け、出力端子に存在する局部発振信号とは逆位相で同
一レベルの補正を加え、局部発振信号の漏れの量をより
小さくすることができる。
FIG. 2 is a block diagram showing a frequency converter according to an example of application of such a circuit. In Figure 2, 24
2 is an intermediate frequency amplification circuit, 241 is an input terminal for intermediate frequency signals, 243 is a local oscillation circuit, 247 is a mixer circuit shown in Fig. 111, 245° and 246 are correction circuits that can vary the phase and level, respectively; The semi-fixed inductance 246 is a semi-fixed resistor. In order to improve the cross-modulation characteristics of the transmission characteristics, the level of the intermediate frequency signal is sufficiently reduced and used within a small signal level range with good linearity. In such a case, the local oscillation level becomes relatively high, and even if the mixer circuit has excellent balance characteristics, the amount of leakage of the local oscillation signal at the output terminal becomes noticeable. In order to correct this, a correction circuit consisting of an inductor 45 and a resistor 46 is provided, and correction is made at the same level and in opposite phase to the local oscillation signal present at the output terminal, thereby further reducing the amount of leakage of the local oscillation signal. be able to.

第2図の場合には、局部発振信号を加える入力端子20
ろにはGaAs−FETによ構成る差動増幅回路がバッ
ファ増幅器として動作し、局部発振回路の方へ漏れ出す
送信信号レベルが十分に小さな値となシ、前記のエコー
歪が十分に小さくなる。
In the case of Fig. 2, the input terminal 20 to which the local oscillation signal is applied
On the other hand, the differential amplifier circuit composed of GaAs-FETs operates as a buffer amplifier, and the level of the transmitted signal leaking toward the local oscillation circuit is sufficiently small, so that the echo distortion described above becomes sufficiently small. .

(発明の効果) 以上説明したように本発明では一対の入力信号端子間に
大きな分離度を得るため、それぞれの増幅回路の出力端
に双対の差動増幅回路を漏れ成分を相互に打消すように
接続することによって平衡性が良好になり、偶数次の混
変調歪が少ないという効果がある。さらに、それぞれの
Q a A s −FETはDC直結形であるため、モ
ノリシックICに適しており、小形化に加えて高信頼化
が容易に達成できるという効果もある。
(Effects of the Invention) As explained above, in the present invention, in order to obtain a large degree of separation between a pair of input signal terminals, a pair of differential amplifier circuits is installed at the output terminal of each amplifier circuit so that leakage components are mutually canceled out. By connecting it to , the balance is improved and even-order cross-modulation distortion is reduced. Furthermore, since each Q a A s -FET is a DC direct-coupled type, it is suitable for a monolithic IC, and has the effect of easily achieving high reliability in addition to miniaturization.

さらに本発明では、GaAs−FETを用いてソース直
列抵抗を省略しているため雑音の発生が少なく、伝送特
性の混変調特性を改善するために中間周波信号レベルを
低減しても出力端子に含まれる熱雑音と局部発振信号レ
ベルとは十分に低く抑えることができる。
Furthermore, in the present invention, since the source series resistance is omitted by using a GaAs-FET, noise generation is small, and even if the intermediate frequency signal level is reduced to improve the cross-modulation characteristics of the transmission characteristics, the noise is not included in the output terminal. Thermal noise and local oscillation signal level caused by this can be kept sufficiently low.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明によるミクサ回路の一実施例を示す回
路図である。 第2図は、第1図に示すミクサ回路を応用した周波数変
換装置の一実施例を示すブロック図である。 第8図は、バイポーラトランジスタによる従来技術によ
って構成した差動増幅回路の一例を丞す回路原理図であ
る。 第4図は、従来技術によるQ a A s −F E 
Tを使用したミクサ回路の一例を示す回路図でおる。 110〜119 、430 ・参・GaAs−FET1
20〜126,246,351.φ52゜431・・・
・・抵抗器 ろ51,352書・・バイポーラトランジスタ242・
・・・・中間周波増幅回路 243・・・・・局部発振回路 245@春・e・インダクタ 247・・・・・きフサ回路 101〜107,202,203,206゜207.2
41,244.401〜403゜406・・・・・端 
子 特許出原人 日本電気株式会社 代理人 弁理士 井ノ ロ   壽 オ)図 才2図
FIG. 1 is a circuit diagram showing an embodiment of a mixer circuit according to the present invention. FIG. 2 is a block diagram showing an embodiment of a frequency conversion device to which the mixer circuit shown in FIG. 1 is applied. FIG. 8 is a circuit principle diagram illustrating an example of a differential amplifier circuit constructed using a conventional technique using bipolar transistors. FIG. 4 shows Q a A s -FE according to the prior art.
This is a circuit diagram showing an example of a mixer circuit using T. 110-119, 430 ・GaAs-FET1
20-126,246,351. φ52゜431...
・Resistor ro 51,352 book ・Bipolar transistor 242・
...Intermediate frequency amplification circuit 243...Local oscillation circuit 245@spring-e-inductor 247...Fusa circuit 101-107, 202, 203, 206°207.2
41,244.401~403゜406... end
Child patent originator: NEC Co., Ltd. agent, patent attorney: Hisao Inoro) Figure 2

Claims (1)

【特許請求の範囲】[Claims] ソースを共通接続した第1および第2のGaAs−FE
Tと、前記第1のGaAs−FETのゲートにゲートを
接続し、前記第1および第2のGaAs−FETのソー
ス共通接続点にソースを接続した第3のGaAs−FE
Tと、前記ソース共通接続点と接地電位点との間に接続
した第1の抵抗器と、前記第1のGaAs−FETのド
レーンにソースを接続した第4および第5のGaAs−
FETと、前記第2のGaAs−FETのドレーンにソ
ースを接続し、前記第5のGaAs−FETのゲートに
ゲートを接続し、前記第4のGaAs−FETのドレー
ンにドレーンを接続した第6のGaAs−FETと、前
記第2のGaAs−FETのドレーンにソースを接続し
、前記第4のGaAs−FETのゲートにゲートを接続
し、前記第5のGaAs−FETのドレーンにドレーン
を接続した第7のGaAs−FETと、前記第5および
第6のGaAs−FETのゲートにドレーンを接続した
第8のGaAs−FETと、前記第8のGaAs−FE
Tのソースにソースを接続し、前記第4および第7のG
aAs−FETのゲートにドレーンを接続した第9のG
aAs−FETと、前記第8および第9のGaAs−F
ETのソースと接地電位点との間に接続した第2の抵抗
器と、前記第8および第9のGaAs−FETのゲート
にゲートを接続し、前記第8および第9のGaAs−F
ETのソースおよび第2の抵抗器の共通接続点にソース
を接続した第10のGaAs−FETとを具備し、前記
第1および第3のGaAs−FETのゲート共通接続点
から第1の周波数の高周波信号を加え、前記第9および
第10のGaAs−FETのゲート共通接続点から第2
の周波数の高周波信号を加え、前記第4および第6のG
aAs−FETのドレーン共通接続点、または前記第5
および第7のGaAs−FETのドレーン共通接続点か
ら前記第1および第2の周波数の高周波信号の和または
差の周波数を有する第3の高周波信号を取出すことがで
きるように構成したGaAs−FETによるミスサ回路
First and second GaAs-FEs whose sources are commonly connected
T, and a third GaAs-FE whose gate is connected to the gate of the first GaAs-FET and whose source is connected to a common source connection point of the first and second GaAs-FETs.
T, a first resistor connected between the source common connection point and the ground potential point, and fourth and fifth GaAs-FETs whose sources are connected to the drain of the first GaAs-FET.
FET, and a sixth GaAs-FET having a source connected to the drain of the second GaAs-FET, a gate connected to the gate of the fifth GaAs-FET, and a drain connected to the drain of the fourth GaAs-FET. a GaAs-FET, a source connected to the drain of the second GaAs-FET, a gate connected to the gate of the fourth GaAs-FET, and a drain connected to the drain of the fifth GaAs-FET; 7 GaAs-FET, an eighth GaAs-FET whose drains are connected to the gates of the fifth and sixth GaAs-FETs, and the eighth GaAs-FET.
T and the source of the fourth and seventh G
9th G whose drain is connected to the gate of aAs-FET
aAs-FET and the eighth and ninth GaAs-FETs
a second resistor connected between the source of the ET and a ground potential point; and a gate connected to the gates of the eighth and ninth GaAs-FETs;
a tenth GaAs-FET whose source is connected to a common connection point between the source of the ET and the second resistor; A high frequency signal is applied, and a second
a high frequency signal with a frequency of
aAs-FET drain common connection point or the fifth
and a third high-frequency signal having a frequency that is the sum or difference of the high-frequency signals of the first and second frequencies from the common drain connection point of the seventh GaAs-FET. Misa circuit.
JP22854184A 1984-10-30 1984-10-30 Mixer circuit Granted JPS61105914A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22854184A JPS61105914A (en) 1984-10-30 1984-10-30 Mixer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22854184A JPS61105914A (en) 1984-10-30 1984-10-30 Mixer circuit

Publications (2)

Publication Number Publication Date
JPS61105914A true JPS61105914A (en) 1986-05-24
JPH0374965B2 JPH0374965B2 (en) 1991-11-28

Family

ID=16878006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22854184A Granted JPS61105914A (en) 1984-10-30 1984-10-30 Mixer circuit

Country Status (1)

Country Link
JP (1) JPS61105914A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912520A (en) * 1987-06-11 1990-03-27 Hitachi, Ltd. (501) Mixer circuit for use in a tuner of a television set or the like
JPH02195705A (en) * 1989-01-24 1990-08-02 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit for television tuner
WO1994016502A1 (en) * 1993-01-13 1994-07-21 Bayruns Robert J Method and apparatus for reducing local oscillator leakage in integrated circuit receivers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494512U (en) * 1972-04-14 1974-01-16
JPS54100617A (en) * 1978-01-26 1979-08-08 Sony Corp Mixer circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494512U (en) * 1972-04-14 1974-01-16
JPS54100617A (en) * 1978-01-26 1979-08-08 Sony Corp Mixer circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912520A (en) * 1987-06-11 1990-03-27 Hitachi, Ltd. (501) Mixer circuit for use in a tuner of a television set or the like
JPH02195705A (en) * 1989-01-24 1990-08-02 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit for television tuner
WO1994016502A1 (en) * 1993-01-13 1994-07-21 Bayruns Robert J Method and apparatus for reducing local oscillator leakage in integrated circuit receivers
US5428837A (en) * 1993-01-13 1995-06-27 Anadigics, Inc. Method and apparatus for reducing local oscillator leakage in integrated circuit receivers

Also Published As

Publication number Publication date
JPH0374965B2 (en) 1991-11-28

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