JPS611057A - Nonvolatile ram - Google Patents

Abstract

PURPOSE:To inexpensively obtain an IC having large memory capacity in high integration by connecting 4-transistor type dynamic RAM with a nonvolatile ROM which can be written with a single power source. CONSTITUTION:When the terminal ERS of an electrically erasable P-ROM101 rises and the signals of a terminal PHIP and a word line WL rise, bit lines BL, -BL are precharged, and Q and Q of a dynamic RAM103 are precharged to ''0'' or ''1''. When the signals of the terminal QP and the line WL rise and the signals of a control gate terminal CG and a select gate terminal SG rise and information of the RAM103 is ''1'' at that time, the charge stored in a capacitor is flowed to a transistor Tr. Thus, the ROM101 becomes rewritable state. The information of the written ROM101 can be returned to the RAM103. According to the circuit configuration, the number of the Trs may be less, and since it is not necessary to provide isolating area, the area of the memory cell can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile RAMK that combines a four-transistor type dynamic RAM cell and a nonvolatile EPROM that can be written to with a single 5V power supply.

Conventional non-volatile RAM (NVRAM) has the disadvantage that it has a large number of elements and a large memory cell area, making it unsuitable for high integration and increasing chip cost.

The present invention aims to eliminate the above-mentioned drawbacks and to obtain an integrated circuit with high integration and large memory capacity.

FIG. 1 shows an actual example of the NVRAM of the present invention, FIG. 2 is a timing diagram, FIG. 5 is a timing diagram, and FIG.
FIG. 4, which is a cross-sectional structure diagram of PROM101, and KPRO
The present invention will be described in detail below with reference to FIG. 5, which shows the characteristics of Mlol.

1) Four transistors, transistors 3 to 6 in FIG. 1, form a dynamic RAM (DRAM) 1'Q3 cell. The operation of DRAM 1 and 3 takes advantage of the high gate impedance of transistor 3 and transistor 4, and applies %0# or 11N to the gate, respectively.
Operation is guaranteed by storing . here 10
〃 is the ground level, and Ki 1 is the VDD level.

In other words, when reading DRAM1'laj, DRAM1'B
When %Ol or %1N information is stored in ,,3,
The bit lines BL and BL are precharged by the terminal φpK, and then, when the word line WL is turned on, the DRA
Since there is a potential difference between BLK and L depending on the information from MIX3, this is done by amplifying this with a sense amplifier (not shown) and outputting it.

Next, for writing to DRAMIX3, voltage is applied to the focus line BL and ELt-%07y or Kame1 according to the write data, and when the word line WL is started, DRAM1
'! Data is written to 11 and 3.

2) Transfer the data of next K DRAMIX3 to K PROM10
The operation of writing to 1 (hereinafter referred to as store operation) is shown in the timing diagram of Fig. 2 and in Fig. 4 K FROMIXl(7)Il.
This will be explained using the fr plane 4-g diagram and the characteristic diagram of F and PROM1X1 in FIG.

Terminal φp, word 1 gland iVL, terminal]l! in FIG. iR
8. Signals to the control gate terminal CG and select gate terminal SG are applied as shown in FIG. The signal at terminal KR8 is transmitted between FOWler-1'lOr(i
It has a high enough voltage to carry the heim current.

When the signal at terminal KR8 rises, Fowler-Nord
The electrons of the floating game FG flow toward the terminal KR8K by the eim current, and after the signal at the terminal ER8 falls, the floating game FG becomes positively charged. This indicates that in the characteristic diagram of K DROMlol shown in FIG. 5, the CK% characteristic of the curve after erasing has shifted from the initial curve a.

Next, when the signal on the terminal φp and the word line WL rises, the bit lines BL and ■1 are precharged, and when the signal on the word line WL rises, the node Q and the node A are restored to the previously stored information. Depending on the situation, it will be precharged to 0 or 11 ki, respectively. When the signal at the terminal φp and the word 'IJWL falls, the signal at the control gate terminal CG and the select gate terminal 8G rises. Since the control gate terminal CG and FG are strongly capacitively coupled, the control gate The floating gate F'G is strongly pushed up by the rise of the signal at the terminal CG, and as a result, a strong electric field is not applied in the y direction in the structural diagram of KFROMIX1 in Fig. 4, and the floating gate F'G is pushed up strongly. When the signal rises, channel t2 becomes conductive.

At this time, the information in DRAM1'9j is stored as
), the node Q is at the %1// level, so when the select gate terminal SG rises, the charge stored in the capacitor 17 flows from the drain of the transistor 7 to the source.

Therefore, in the cross-sectional structure diagram of the EPROMjol shown in FIG. 4, electrons are rapidly accelerated near the boundary between channel t1 and channel L2, and since an electric field is applied in the y direction, electrons jump into the floating FGK with a certain probability.

floating game) FG is negatively charged and K F in Figure 5
In the characteristic diagram of ROMlol, the characteristics shift from the curve C showing the erased state to the curve showing the written state.

On the other hand, the information of DRAM1'Ek3 is 0 (store 0
), the node (is at the %0 level, there is no charge in the capacitor 17, and no current flows through the transistor 7 even if the signal at the select gate terminal SG rises).

Therefore, since electrons are not written into the floating gate 7', the curve C representing the erased state in the characteristic diagram of EpROMIQl in FIG. 5 remains as it is.

Control game) terminal CG and select gate terminal SG
The writing of data to Eli PROMlX1 is completed by the fall of the signal.

3) Recall operation: The operation of returning the fc information written to the non-volatile K PROM 101 to the DRAM1\3 is called a recall operation. Recall operation timing diagram Figure 5 and B
This will be explained using Figure 5, which shows a custom-made PROM11.

Pi FROM1 now written by store%11K
When returning the information of X1 to DRAM1'a, 3, the terminal φp
When the word and %lWL signals rise, the nodes A and Q of the DRAMIX5 cell are precharged to 1, respectively. When the signal on the terminal φp and the word line WL falls and the signal on the select gate terminal 8G rises, the characteristics of the K FROMIX1 are as shown in the write state in Figure 5, when the signal on the control gate terminal CG becomes Ov. No current flows between this and the drain north of transistor 7. Therefore, the node Q is kept at '1' f, and the node value remains %11, but the node Q has a capacitor of 1.
7 is connected and has a large amount of charge, so in the end the node Q
The discharge becomes faster, and node Q becomes '11' and node A becomes '0'.

On the other hand, E FROM written by store %O#
The characteristics of IXl are shown by the curve C showing the erased state in the characteristic diagram 5.
As shown in the figure, even when the signal at the control gate terminal CG is 0■, the current flows. Therefore, when the signal at the select gate terminal SG rises in the node Q between the node Q and the node Q, which have reached the %1N level due to precharging, a current flows from the drain of the transistor 7 to the source, and the node Q becomes %QI level. In this way, DR when storing
The information of AM1X3 is stored in Bli PROMIXI K, and by the recall operation, the information of B FROMlol is recalled again to DRAM1'aj [DRA at the time of storage.
MIX3 information can be reproduced.

Furthermore, since the information in the K PROMI note 1 is non-volatile, it will not disappear even if the power is turned off.

As described above, the present invention can be used as a nonvolatile RAM. It also requires fewer transistors than conventional circuits,
Moreover, unlike CMOS static RAM, there is no need to provide an isolation region for separate wells, so the area of the memory cell can be small.

Therefore, if the present invention is used to increase capacity or reduce chip cost, it will be very effective.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an embodiment of the non-volatile RAM of the present invention, Figure 2 is a timing diagram of a store operation from DRAM to E2PROΔ1 of the present invention, and Figure 3 is a recall operation from 2F ROM to DRAM of the present invention. FIG. 4 is a cross-sectional structural diagram of the E2F ROM cell, and FIG. 5 is a characteristic diagram of the 2F ROM cell. 3...N channel MOS) transistor 4...
N5...N6...N7...N8...P9...P10...N11...First polycrystalline silicon 12...P substrate 15...・N diffusion layer 14...N diffusion layer 15...N diffusion layer 16...Second polycrystalline silicon 17...Capacitor 100---SRA M2O3...E2PRM 102...Memory Cell 103...4Tr dynamic RAM or more

Claims (2)

[Claims] (1) 4 consisting of 4 single-channel MOS transistors
A non-volatile RAM characterized by connecting a transistor-type dynamic RAM and a non-volatile ROM that can be written to with a single 5V power supply. (2) At the connection point between the output of the RAM and the ROM,
The nonvolatile RAM according to claim 1, characterized in that a capacitor is connected.