JPS61105117A - Logic circuit - Google Patents

Abstract

PURPOSE:To improve the load driving capability and to attain high speed, low power consumption and high circuit integration by constituting a driver as an inverter circuit of E/D constitution and a buffer receiving an output of the said inverter circuit as a source follower circuit of E/D constitution without level shift to obtain a logical output of the input inputted to the inverter circuit from the source follower circuit. CONSTITUTION:When a high level voltage is inputted to the input, a voltage of a low level appears at a connecting point 4 and the low level voltage is outputted from a connection point 6 while keeping the corresponding level. Even when the input level is converted, the similar function is executed. Since the diode characteristic of the gate input of the next stage does not almost appear through the operation above, the drive capability at the leading is increased and the drive capability can be increased similarly because the characteristic changes at a low resistance region at the trailing. Further, in case of the VON state, the diode current of the gate of next stage is zero and in case of the VOL state, the source follower power is zero, then the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in logic circuits using field effect transistors.

There are various types of semiconductor logic circuits.

This type of logic circuit is often implemented as an integrated circuit. Therefore, logic circuits must be suitable for integration.

In addition, when the logic circuit is composed of unit logic circuits, the power consumption is low (low power supply voltage), and the power supply that supplies the power is smaller, from the viewpoint of increasing suitability for integration as described above. good. In addition, such unit logic circuits are required to have little delay, high-speed operation, high load driving ability, high logic function, and high margin.

[Conventional technology]

As a conventional unit logic circuit, /D as shown in Figure 6
There is one that consists of an inverter circuit with a D/D configuration and a source follower circuit with a D/D configuration connected to the other output. Also, the seventh
There is also an inverter circuit with the /E configuration as shown in the figure.

[Problem that the invention seeks to solve]

Since the conventional circuit shown in FIG. 6 has a D-FET configuration, it requires two power supplies and requires a level shift in its source follower circuit. Also, the power supply voltage is IVDD l, IVEE
The power consumption was high as l was 3 to 5 volts or more, and the logic function was also low (FI = 8, FO = 8 or more, output source dots: 2).

, In addition to these defects, the load driving ability is poor.

This is because the diode (characteristics) of the input FET of the next stage gate circuit is
Since the load drive current is operated at a point where the output voltage is sufficiently visible, most of the load drive current is spent as a diode current during the rise of the output, resulting in a deterioration of the load drive ability. Since the D/D configuration has a circuit configuration in which the current source works sufficiently even in the VOI state, the driving ability at the falling edge is inferior (see (2) in Figure 2).
-1)). Also, as mentioned above, it is not possible to increase the number of output dots when the source follower circuit is D-FE when the output is VOH.
Because it is a T configuration, the decrease in VGS (increase in VOH) becomes large, so the diode current in the next stage increases, and when the output is VOL, VOL rises, and the margin on the low level side disappears. It is.

Furthermore, in the conventional circuit shown in FIG. 7, since the margin on the VOL side is generally small (see (3-1) in FIG. 3), the logic function is FI<4. It is small, FO≦4, and cannot produce an output dot due to the circuit configuration. Further, like the conventional circuit shown in FIG. 6, the diode current of the gate input of the next stage flows in the VOH state, so power consumption tends to increase, and the drive ability at rise is poor.

Also, VDD is set to IVDDI≦2Vp (Vp is MESF
It is the forward voltage (VGS) of ET. ) If the voltage is lowered to such a degree, the driving ability particularly at the rising edge will deteriorate, and the rising and falling driving abilities will become unbalanced.

[Means for Solving the Problems J] The present invention provides a logic circuit capable of solving the above-mentioned technical problems as much as possible, and its means include a first enhancement type field effect circuit having an input connected to a gate. An inverter circuit including a transistor and a first depletion type field effect transistor whose gate and source are directly connected to the drain of the transistor, and a second enhancement type field effect transistor whose gate is connected to the connection point of both transistors constituting the inverter circuit. a source follower circuit comprising a field effect transistor and a second depletion type field effect transistor in which a drain is connected to the source of the transistor and a gate and a source are directly connected; the first depletion type field effect transistor and the second depletion type field effect transistor; a circuit for supplying power to the drain of an enhancement mode field effect transistor and the sources of the first enhancement mode field effect transistor and the second depletion mode field effect transistor, and the connection of both transistors constituting the source follower circuit; It is configured to output points.

[Effect]

According to the circuit of the present invention, the driver is D/E +j
An inverter circuit with an E configuration is used, and the circuit that receives the output of this inverter circuit is configured as a source follower circuit with an E/D configuration without level shift, so that the logical output of the input input to the inverter circuit is obtained from the source follower circuit. Because of its high load driving capacity and high speed,
In addition to low power consumption (low power supply voltage) and high logic function, it is possible to use a single power supply, and the margin can be sufficiently high, making it possible to obtain a logic circuit that can be highly integrated.

[Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. In this figure, 1
2 is a first enhancement type field effect transistor whose input is connected to the gate, and 2 is a first depletion type field effect transistor whose gate and source are directly connected to the drain of the transistor 1. These transistors 1 and 2 constitute an inverter circuit. 3 is a second enhancement type field effect transistor in which the connection point 4 of transistor 1゜2 is connected to the gate, and 5 is a second depletion type field effect transistor in which the drain is connected to the source of transistor 3, and the gate and sort are directly connected. It is a type field effect transistor. Transistor 3.5 constitutes a source follower circuit. The connection point 6 of the transistor 3.5 serves as the output of the entire circuit.

Further, transistors 1, 2, and 3.5 have VthE=0 to 0.
It is a MES field effect transistor (hereinafter abbreviated as MESFET) of 3 volts and Vtho = -1.0 to -0.3 volts. The drain of the transistor 2.3 is given a reference potential, for example, the ground potential, and the sources of the transistors 1 and 5 are given a voltage VDD [this vDD is I
VDDI<2VP (VF is the forward voltage of MESFET (
VGs). ) (Transistor (E-FET)
1 VF+transistor (E-FET) 3 Vp). ], for example, -1 and 2 volts are supplied, so that there is only one power supply. Furthermore, although the gate width and threshold voltage V, th of each transistor are parameters for causing the circuit of the present invention to operate as desired, these values in FIG. Then, the gate widths of transistors 2 and 3.5 are Wo /2.2Wo and 2Wo, respectively, the Vth of transistor 1.3 is +0.1 volt, and the Vth of transistor 2.5 is -0 and 5. It's a bolt.

The circuit of the present invention constructed in this way performs the function of an inverter circuit as a whole. That is, when a high-level voltage is input to the input, a low-level voltage appears at the connection point 4, and this low-level voltage is transmitted from the connection point 6 via the source follower circuit (buffer) to maintain its corresponding level. Output. The same function is achieved even when the input level is reversed.

In the circuit of the present invention that operates in this way, the IVDD
I≦2VF, and therefore the diode characteristics of the gate input of the next stage are almost invisible, so (2-
As shown in 2), the drive capacity at startup is large,
In the case of falling, the resistance is in the low resistance region ((2, -2 in Figure 2)
(see), so the drive capacity can be similarly increased (see). Note that the E/D in (2-2) in Figure 2
The source follower current of the configuration is ID5 of E-FET (3)
= IDS I of D-FET (5), and (
The source follower current of the D/D configuration in 2-, 1) is ■Ds of the source follower D-FET = I of the current source D-FET
D5I 10th stage gate circuit manual power - FET gate current I
GS (diode current).

Also, in the VOH state, the diode voltage i=o of the next stage gate
In the VOL state, the source follower power is O, so that the power consumption required to obtain the same performance (driving ability) can be lower than that of the conventional circuits shown in FIGS. 6 and 7.

Also, since the source follower circuit has the circuit configuration as described above, ■OL is at least 1V of the enhancement transistor 3 of the source follower circuit compared to the circuit shown in FIG.
The margin improves only in the voltage bone of thl ((3 in Figure 3)
-2)).

Furthermore, a source follower circuit with an E/D configuration is used as a buffer,
Since IVDDI≦2VF, there is a decrease in VGS of the source follower circuit when the output is VOH, but E-FE
By using T, the ratio is small, the diode current in the next stage is small, and when the output is VOL, the source follower current becomes zero and VOL does not rise, so the output is more than twice that of the conventional circuit (Figure 6). A source follower dot is obtained (see Figure 4).

In addition, by arbitrarily changing the gate width ratio of the E-FET and D-FET of the D/E configuration inverter circuit and the E/D configuration source follower circuit, the rise/fall delay time (including drive capacity) ratio In an optimal design, the rise/fall delay time ratio can be set to Σ1.

FIG. 5 shows another embodiment in which the above parameters are changed.

Furthermore, since the circuit of the present invention has fewer elements (no diodes) than the conventional circuit, it is suitable for high integration.

In addition, the circuit of the present invention can not only perform AND (and vertical product) (the number is 2) of inputs, but also can configure a circuit by connecting a large number of source follower circuits to an inverter circuit (
multi-source follower circuit output). Also, if the voltage range is around IVDDI≦2VF (≦1.5 volts), separate the inverter circuit power supply and source follower circuit power supply, and set the source follower circuit power supply in the negative direction a little deeper than the inverter circuit power supply. , and each FET
By appropriately combining the Vth and gate width of , it is possible to similarly realize the purpose of the circuit of the present invention described above.

Also, the field effect transistor may be an MO3 field effect transistor.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to: 1) increase the load driving capacity (and thereby promote lower power consumption); 2) increase the logic function while promoting faster operation speed; In addition to being able to use a single power source and achieving higher margins, it also allows for higher integration.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an embodiment of the present invention, and Figure 2 (2-1
) is the source follower current (VDS-IDS of the circuit in Figure 6)
Figure 2 (2-2) is a diagram showing the source follower current (VDS-IDS characteristics) of the circuit in Figure 1, and (3-1) in Figure 3 is the VIN of the circuit in Figure 7. -The diagrams showing the VOUT characteristics, Figure 3 (7) (3-2) are the circuits in Figure 1 ("V
A diagram showing rN-VOUT characteristics. Figure 4 is a diagram showing a circuit in which a large number of source follower dots are obtained from the source follower circuit of the circuit in Figure 1. Figure 5 is a diagram showing a case where the parameters of the circuit in Figure 1 are changed. FIG. 6 is a diagram showing one conventional circuit, and FIG. 7 is a diagram showing another conventional circuit. In the figure, 1.3 is an enhancement type field effect transistor, and 2 and 5 are depletion type field effect transistors. Figure 8 Cause 4 Figure 5 Figure 61 Figure 7 Procedural amendment (voluntary) 1°l Table of 11, BA Showa S2; Related Patent Applicant Address: 1015 I-J-liJ Naka (52
2) 81U; Fujitsu Limited 4 Agent IL Office 1, Nakahara-ku, Yozaki City, Kanagawa Prefecture. Small (Address 1015 of 11 Description (full text correction) 1. Title of the invention Logic circuit 2. Claims (11) A first enhancement type field effect transistor having an input connected to the gate, and a gate and a drain connected to the drain of the transistor. an inverter circuit having a first depletion field effect transistor directly connected to the source;
A second enhancement type field effect transistor in which the connection point of both transistors constituting the inverter circuit is connected to the gate, and a second depletion type field effect transistor in which the source drain of the transistor is connected and the gate and the source are directly connected. a source follower circuit having a source follower circuit, and supplying power to the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor and the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor. a logic circuit configured to output a connection point between both transistors constituting the source follower circuit. (2) V is the output voltage of the inverter circuit when a predetermined old gh level is applied to the input. LM + the power supply voltage supplied to the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor; V D Or the threshold voltage of the second enhancement type field effect transistor;
, 1. When closed, (VoLM -VI, +) < V. The logic circuit according to claim 1, characterized in that: (3) The field effect transistor is a MES field effect transistor, and the power supply circuit connects the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor to a first potential, and 1 as a reference potential, the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor are connected to a voltage VDfl lower than the reference potential, and the voltage VDD is jVonj < 2. Vy (VF is ME
This is the Schottky diode forward voltage between the gate and source of the S field effect transistor. ) The logic circuit according to claims 1 and 2, characterized in that the logic circuit has the following features. (4) The logic circuit according to claims 1 and 2, wherein the field effect transistor is a MIS field effect transistor. 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to improvements in logic circuits using field effect transistors. There are various types of semiconductor logic circuits. This type of logic circuit is often implemented as an integrated circuit. Therefore, logic circuits must be suitable for integration. In addition, when the logic circuit is composed of unit logic circuits, the power consumption is low (low power supply voltage), and the power supply that supplies the power is smaller, from the viewpoint of increasing suitability for integration as described above. good. In addition, such unit logic circuits are required to have little delay, high-speed operation, high load driving ability, high logic function, and high margin. [Prior Art] As a unit logic circuit using a conventional MES field effect transistor (Schottky junction field effect transistor/MESFET), a driver transistor and a load resistor as shown in FIG. 6 are connected to a depletion type field effect transistor (D- An inverter circuit (hereinafter referred to as D
/D configuration inverter circuit. ) and a source follower transistor using a depletion field effect transistor connected to its output, l bell shift diode,
and a source follower circuit (hereinafter referred to as a D/D configuration source follower circuit) configured from a current source using a depletion type field effect transistor. Furthermore, an inverter circuit (hereinafter referred to as an inverter with an E/D configuration) is constructed using an enhancement type field effect transistor (E-FET) as a driver transistor and a depletion type field effect transistor as a load resistor, as shown in Fig. 7. (referred to as a circuit). Further, the source follower transistor of the D/D configuration source follower circuit connected to the E/D configuration inverter circuit and its output as shown in FIG. 8 is an enhancement type field effect transistor, and the level shift diode is 1.
There is also a source follower circuit consisting of one or two source follower circuits (hereinafter referred to as a source follower circuit with an E/D configuration with level shift). Further, as shown in FIG. 9, an inverter circuit with an E/D configuration and an enhancement mode field effect transistor is used as the current source of the E/D source follower circuit at its output, and a source follower circuit (hereinafter referred to as E/D) without a level shift diode is used. E
This configuration is called a source follower circuit. ). [Problems to be Solved by the Invention] Since the conventional circuit shown in FIG. 6 has a D-FET configuration, it requires two power supplies and requires a level shift in its source follower circuit. Also, power supply voltage 1vooj, IVEE
I is high at 3 to 5 ports or more, and power consumption is large, and the logic function is FI = 8. While FO=8, the output logic function is low, with output source follower dots (hereinafter referred to as output dots) ~2. In addition to these defects, the load driving ability is poor. This is the output voltage ■. In order to have a large margin on the side of This is because the source follower circuit is a D/D with a level shift diode.
Since the circuit configuration is such that the current source functions sufficiently even in the VOL state, the driving ability at the time of falling is inferior. (See (2-1) in Figure 2). Also, as mentioned above, if the number of output dots cannot be increased, the output is ■. When H, the source follower circuit has a D-FET configuration, so the decrease (■.8 increase) in the gate-source voltage VCS of the source follower transistor is large (as a result, the diode current in the next stage becomes large). Yes, the output is ■
. , when V. This is because L increases and the margin on the low level side disappears. In addition, in the conventional circuit shown in FIG. 7, V is generally applied. Since the margin on the L side is small (see (3-1) in Figure 3), the logic function is Fl<4. The FO<4 is small, and the output dot cannot be obtained due to the circuit configuration. Further, like the conventional circuit shown in FIG. 6, the diode current of the gate input of the next stage flows in the VO operation state, so power consumption tends to increase, and the drive ability at the start-up is poor. Also, Vonwo l Van l < 2 VF
(VF is the forward voltage of the Schottky diode between the gate and source of MESFET 17). Hereinafter, it will be referred to as ■. ) If the voltage is lowered to such a degree, the driving ability particularly at the rising edge will deteriorate, and the rising and falling driving abilities will become unbalanced. Another conventional example is a logic circuit consisting of an inverter circuit and a source follower circuit as shown in FIG. 6, but in which a portion of the depletion type field effect transistors are replaced with enhancement type field effect transistors. One example of these is a circuit consisting of an E/D configuration inverter circuit shown in FIG. 8 and an E/D configuration source follower circuit with a level shift diode, and a circuit consisting of an E/D configuration inverter circuit and an E/E configuration shown in FIG. 9. This circuit consists of a source follower circuit. In these conventional examples, since enhancement type field effect transistors are used, the power supply voltage can be lowered somewhat compared to the conventional example shown in FIG. 6, but they have the same drawbacks. That is, in the conventional example shown in FIG. 8, the output is V. When +4, current (diode current) flows to the next stage. Also, since there is a level shift diode in the source follower circuit, the power supply voltage v
oo cannot be set to l VD, +≦2VF, and in order to obtain optimal performance, approximately 3VF (~2.5V) is required for 1D. Furthermore, since it is a source follower circuit with a level shift diode, the driving ability is somewhat degraded. In the conventional example shown in FIG. 9, the output is ■. When □, diode current flows to the next stage. Also, the output is ■. When the current is L, current flows through the source follower circuit, and when the output dot is taken, the output becomes ■ as in the case described above (Fig. 6). ■ At 1. L rises ■. , the margin on the side decreases. An enhancement type field effect transistor is used as the source follower transistor, and the rate of increase in VOt is
Although it is smaller than the above (Figure 6), this ■. , the number of output dots is limited due to the increase in . Also, in order to obtain optimum performance, the power supply voltage should be 2VF<lv. About 1ヱ2■ is necessary. The output is ■. At the time of A, the diode current flows to the next stage, and at the time of VOt, the current flows to the source follower circuit, so the load driving ability is poor. In this way, since there is a limit to reducing the power supply voltage in both the conventional examples shown in FIGS. 8 and 9, there is also a limit to reducing power consumption. [Means for Solving the Problems] The present invention provides a logic circuit capable of solving the above-mentioned technical problems as much as possible, and the means thereof include a first enhancement type field effect whose input is connected to the gate. An inverter circuit including a transistor and a first depletion type field effect transistor whose gate and source are directly connected to the drain of the transistor, and a second enhancement type field effect transistor whose gate is connected to the connection point of both transistors constituting the inverter circuit. a source follower circuit comprising a field effect transistor and a second depletion type field effect transistor having a drain connected to the source of the transistor and a gate and a source directly connected; the first depletion type field effect transistor and the second depletion type field effect transistor; a circuit for supplying power to the drain of an enhancement mode field effect transistor and the sources of the first enhancement mode field effect transistor and the second depletion mode field effect transistor, and the connection of both transistors constituting the source follower circuit; It is configured to output points. [Operation] According to the circuit of the present invention, the driver is an inverter circuit with an E/D configuration, and the buffer that receives the output of the inverter circuit is configured as a source follower circuit with an E/D configuration without level shift. Since the logic output of the human input input to the source follower circuit is obtained from the source follower circuit, it has high load driving capability, high speed, low power consumption (low power supply voltage), high logic function, and can be reduced to a single power supply, reducing margins. It is also possible to obtain a logic circuit band that is sufficiently high and suitable for high integration. [Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of the invention. In this figure, 1
2 is a first enhancement type field effect transistor whose input is connected to the gate, and 2 is a first depletion type field effect transistor whose gate and source are directly connected to the drain of the transistor l. These transistors 1.2 constitute an inverter circuit. 3 is a second enhancement type field effect transistor in which the connection point 4 of transistor 1゜2 is connected to the gate, and 5 is a second depletion type field effect transistor in which the drain is connected to the source of transistor 3, and the gate and source are directly connected. It is a type field effect transistor. Transistor 3.5 constitutes a source follower circuit. The connection point 6 of the transistor 3.5 serves as the output of the entire circuit. Further, the threshold voltages of transistors 1, 2, and 3.5 are Vth, =0 to 0.3 volts, (2). -1.0~
- below 0.3 volt MES field effect transistor C,
It is abbreviated as MESFET. ). A reference potential, such as the ground potential, is applied to the drain of the transistor 2.3, which is a transistor (Vas), and the value is generally 0.7 to 0.8 V in the case of G, A, and MESFETs.
a) (VF of transistor (E-FET) 1
+l-transistor (E-FET) 317)VF')
Toru. ], for example, -1 and 2 volts are supplied, so that there is only one power supply. Furthermore, the gate width and threshold voltage of each transistor are parameters that enable the circuit of the present invention to operate as desired.
These values in FIG. 1 define the gate width of transistor l as W. When closed, the gate widths of transistor 2°3.5 are wo / 2, 2 wo, and 2W0, respectively, transistor 1.3 (7) Vtk is +0.1 volt, and vth of transistor 2.5 is -0°5 volts. Each of these parameter values represents the voltage appearing at the output 4 of the inverter circuit when a predetermined old gh level is applied to the input 1. LH, the threshold voltage of the transistor 3 constituting the source follower circuit is set to Vthe+1st
When the power supply voltage in the configuration shown in the figure is VDD, (VOL
NV. D) <V. This is an example of satisfying the following. The circuit of the present invention constructed in this way performs the function of an inverter circuit as a whole. That is, when a high-level voltage is input to the input, a low-level voltage appears at the connection point 4, and this low-level voltage is transmitted from the connection point 6 via the source follower circuit (buffer) to maintain its corresponding level. Output. And it will perform the same function even if the human power level is reversed. In the circuit of the present invention that operates in this way, 1vDD
1<2v, and therefore the diode characteristics of the gate input of the next stage are almost invisible.
-2), the driving capability at the time of rising is large, and in the case of rising, the resistance is in the low resistance region ((2-2 in Figure 2)
), the driving capacity can be similarly increased. Note that the source follower current of the E/D configuration in (2-2) of FIG. 2 is E - F E T (3) ID5=D-
FET (51 I.Sl, (2-4 in Figure 2)
), the source follower current of the D/D configuration of the conventional example (Fig. 6) is II of the source follower D-FET, s = electric 'IJ
■ of JJD-FET. , I Tenth stage gate circuit input - FET gate current ■6. (diode current). Also, in the VO state, the diode current of the next stage gate = 0
In the VOL state, the source follower electric car becomes 〇, so the power consumption required to obtain the same performance (driving ability) is lower than that of the conventional circuits shown in Figs. 6, 7, 8, and 9. be able to. Further, since the source follower circuit has the circuit configuration as described above, VOL is at least lower than lv of the enhancement transistor 3 of the source follower circuit, compared to the circuit shown in FIG.
The margin is better for voltage bone 1 ((3-) in Figure 3.
2)). Utilizing this fact, as mentioned above, when the predetermined old gh level is applied to the human power 1 of the circuit shown in FIG. 1, the output voltage of the inverter circuit is calculated as follows. When the threshold voltage of LN+ source follower transistor is "1. hll+ll type pressure is ■, D, (VOLN VDD) <Vth
By setting e, the output becomes V. Source follower circuit current ID5 at L time = 0. V. t: VDn. Furthermore, a source follower circuit with an E/D configuration is used as a buffer,
Since IV, l<2V, the output is ■ when the output is dot. When , there is a decrease in the VCS of the source follower transistor in the source follower circuit, but the proportion is small due to the use of E-FET, the diode current in the next stage is small, and the output is ■. When it is L, the source follower circuit becomes zero and ■. , does not rise, so an output source follower dot more than twice as large as that of the conventional circuit (FIGS. 6 and 9) can be obtained (see FIG. 4). In addition, by arbitrarily changing the gate width ratio of the E-FET and D-FET of the E/D configuration inverter circuit and the E/D configuration source follower circuit, the rise/fall delay time (including drive capacity) ratio can be varied, and in an optimal design the rise/fall delay time ratio can be set to ~1. FIG. 5 shows another embodiment in which the above parameters are changed. Furthermore, since the circuit of the present invention has fewer elements (no diodes) than the conventional circuits (FIGS. 6 and 8), it is suitable for high integration. Note that the circuit of the present invention is an AND (vertical product) of inputs (the number ~
In addition to 2), it is also possible to configure a circuit by connecting a large number of source follower circuits to an inverter circuit (a multi-source follower circuit output can be obtained). Also, I
If VIID I < 2 VF, separate the power supply of the inverter circuit and the power supply of the source follower circuit, make the power supply of the source follower circuit slightly deeper than the power supply of the inverter circuit in the negative direction, and set the depth and gate width of each FET. By appropriately combining them, it is possible to similarly realize the purpose of the circuit of the present invention described above. Further, the field effect transistor is a Mis field effect transistor (Metal In5ulator Sem1con).
duction field effect transistor/MISFET)
It may be. When using MIS field effect transistors, a source follower circuit with an E/D configuration without level shift is connected to an inverter circuit with an E/D configuration, and as described above (VOLN
By setting VDD) <V, low power consumption,
High load driving capability and a large number of output dots are obtained. As can be seen from the explanations so far, Figs. 1, 5 to 9 show the number of inputs of each logic circuit and the applied power supply voltage (G
Of course, ND can be set to +van, and van can be set to GND). [Effects of the Invention] As described above, according to the present invention, ■ it is possible to increase the load driving capacity and promote lower power consumption, and ■ it is possible to achieve higher logic functions while promoting faster operation speed. In addition, the following effects can be obtained: 1) It is possible to use a single power supply, resulting in a high margin, and 2) It is suitable for high integration. 4. Brief description of the drawings Fig. 1 shows an embodiment of the present invention, and Fig. 2 (2-1) shows an embodiment of the present invention.
) is the source follower current of the circuit in Figure 6 (■□-I I,
(2-2) in Figure 2 is a diagram showing the source follower current (5ros characteristic) of the circuit in Figure 1, (3-1) in Figure 3 is a diagram showing the source follower current (5ros characteristic) in the circuit in Figure 7. A diagram showing the VIN vout characteristics, (3-2) in Figure 3 shows the V and N of the circuit in Figure 1.
-V. Figure 4 shows a circuit that obtains a large number of source follower dots from the source follower circuit of the circuit in Figure 1. Figure 5 shows a circuit when the parameters of the circuit in Figure 1 are changed. FIG. 6 is a diagram showing one conventional circuit, and FIGS. 7 to 9 are diagrams showing other conventional circuits. In the figure, 1.3 is an enhancement type field effect transistor, and 2.5 is a depletion type field effect transistor. (-t? 4V) (-z, 4V) Boiling θ diagram q diagram

Claims (3)

[Claims] (1) an inverter circuit including a first enhancement type field effect transistor whose input is connected to the gate and a first depletion type field effect transistor whose gate and source are directly connected to the drain of the transistor;
a second enhancement type field effect transistor in which the connection point of both transistors constituting the inverter circuit is connected to the gate; and a second depletion type field effect transistor in which the drain is connected to the source of the transistor and the gate and the source are directly connected. a source follower circuit having a drain of the first depletion type field effect transistor and the second enhancement type field effect transistor, and a source of the first enhancement type field effect transistor and the second depletion type field effect transistor. a logic circuit comprising a circuit for supplying power, and configured such that a connection point between both transistors forming the source follower circuit is an output. (2) The field effect transistor is a MES field effect transistor, and the power supply circuit connects the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor to ground potential, and The sources of the enhancement mode field effect transistor and the second depletion mode field effect transistor are connected to a voltage V_D_D lower than ground potential, where the voltage V_D_D is |V_D_D|
2. The logic circuit according to claim 1, wherein the voltage is set to ≦2V_F (V_F is the forward voltage of the MES field effect transistor). (3) The logic circuit according to claim 1, wherein the field effect transistor is a MOS field effect transistor.