JPS61104388A - Defective loop data processing method of magnetic bubble memory device - Google Patents

Abstract

PURPOSE:To shorten a read-out time of a defective loop data by storing a defective minor loop stored in a boot-loop in a minor loop, in a RAM. CONSTITUTION:When an access is executed to a magnetic bubble memory device 1 by a host system 5, all defective minor loops of all blocks stored in a boot-loop in a minor loop of the device are read out by the first access and written in a RAM4 through a controller 3. Accordingly, even when the access extends over two blocks, it is unnecessary to read out a defective loop on the boot-loop each time, and a read-out time of a defective loop data is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for processing defective loop data in a magnetic bubble memory device.

[Conventional technology]

Some magnetic bubble memory devices are constructed by combining a plurality of blocks into one chip. In this case, each block includes a plurality of minor loops and one boot loop that stores which minor loop is defective, as is well known.

FIG. 2 shows an example of the configuration of a 4 megabit chip.

As shown in the figure, a 4-megabit chip 1 is constructed by combining four blocks #0 to #3, each having a capacity of 1 megabit, and each block #0 to #3 is a boot block indicated by diagonal lines in the figure. Loop BL (10) to BL (13
).

FIG. 3 is a circuit diagram showing one block #0 of the well-known magnetic bubble memory device shown in FIG.

In the same figure, ML(0), ML(1), -, ML(5
83) is a minor loop, each effective minor loop can contain a bubble of 2048 bits, so a 1 Mbit device consists of 2048 pages, thus 1
Megabit devices are configured. BL (10
) is a boot loop with 584 minor loops ML(0), ML(11,-., ML(583)
It remembers which one is defective. Also, RMJ
is the read major line, WMJ is the write major line, RG is the replicate gate, SW is the swap gate, BRG is the boot replicate gate, BSG is the boot swap gate, DET is the detector, GEN is the generator, XC is the X drive coil, YC is the Y Drive coil, E
C is a cancellation coil, all of which are well known. Other blocks #1 to #3 also have the same configuration as #O.

A conventional defective loop data processing method will be explained with reference to FIG. As shown in FIG. 5, conventionally, each time a block is accessed, the defective loop data stored in the boot loop of that block is stored in a RAM (not shown) at the beginning of the access. . For example, as shown in the figure, access to the magnetic bubble memory device 1 is performed on block #0, 7'lock #2. Pro Tsuk #0
．． When block #1 and block #3 are executed in this order, in step A, the boot loop B L (
The defective loop data written in t0 in 110) is
A controller (not shown) manages the minor loop M L (0) to ML (
583) Read out the necessary data of the loops excluding the defective loop (FIG. 3) to the host system. Next, in step B, the boot loop B L (112) of block #2
After writing the defective loop data to the RAM, the necessary data of block #2 is read out to the host system in the same manner as above. After this, block #0 is accessed again in step C, but the boot loop B L (
110) data is already in the boot loop B L (#2)
Since it has been rewritten on the RAM by
A procedure for storing it in AM is required.

After reading the defective loop data of the boot loop B L (+10) with the step knob C, read the necessary data of the block #O.
Then, in step D, the defective loop data and normal data of block #1 are read in the same manner as above, and in step E, the defective loop data and normal data of block #3 are read in the same manner as above.

[Problems to be solved by the invention]

According to the above conventional method, the defective loop data is read from the corresponding boot loop for each block to be accessed, so after accessing one block on one chip, other blocks are accessed, and then Even if one block is accessed multiple times with accesses to other blocks, such as accessing one block again, the defective loop data on the boot loop must be read each time, and the defective loop There is a problem that it takes a long time to read data.

[Means to solve problems]

An object of the present invention is to solve the above-mentioned problems and shorten the reading time of defective loop data, and for this purpose, all defective loop data of all blocks are read out at the first access to a chip of a magnetic bubble memory device. One block is accessed multiple times by storing the bad loop data of all blocks in a RAM that can store it, and then reading out the data on minor loops other than the bad loops of each block under the control of the controller. However, a method for processing bad loop data in a magnetic bubble memory device is provided that eliminates the need to access the boot loop other than the first access to the boot loop.

[Operation] Since the defective loop data of all blocks is read out to the RAM in advance, there is no need to read the defective loop data every time each block is accessed, and the time for reading the defective loop data is shortened.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 and 4.

FIG. 1 is a flowchart showing a method for processing bad loop data according to an embodiment of the present invention, and FIG. 4 is a block diagram showing an apparatus for implementing the method shown in FIG. In this embodiment as well, it is assumed that the magnetic bubble memory device 1 shown in FIG. 2, which constitutes one chip with 4 megabits, is used.

1 and 4, in step A, during the first access to the magnetic bubble memory device 1 under the control of the host system 5, the boot loop of all blocks #0 to #3 is performed B L (#O) to B L All the defective loop data stored in (13) is outputted and serially stored in the RAM 4 via the direct peripheral circuit 2, indirect peripheral circuit (controller) 3, and data line. In this case, the controller 3 controls the write timing for the RAM 4 via the timing control line T. The RAM 4 has a capacity sufficient to store four blocks of defective loop data.

Next, in step B, the controller 3 refers to the defective loop data and executes the minor loops ML(0) to ML.
(583), out of a total of 2048 pages, the necessary data is read out from the data of all loops excluding the defective loop and sent to the host system 5. Next, in step C, the normal data of block #2 is immediately read to the host system 5 without reading the defective loop data from block #2 as in the conventional case. Hereinafter, in steps D, E, and F, the defective loop data is block #0. block#
Normal data is continuously output to the host system 5 without being read from block #1 and block #3. In this way, even though block #0 is accessed twice, the defective loop data only needs to be read once the first time.

In the above embodiments, an example in which one chip is composed of four blocks has been described, but the present invention is not limited to this, and can of course be applied to a case in which one chip is composed of any number of blocks. Further, the same effects of the present invention can be obtained even if any of blocks #0 to #3 is accessed multiple times.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, (■) All defective loop data of all blocks are read in advance at the first access to the bubble memory device, so even if the access spans between blocks, booting is possible. It is no longer necessary to read out defective loop data on a loop each time, and the time required to continuously read defective loop data is shortened.

In particular, even if the same block is accessed multiple times, the bad loop data only needs to be read the first time.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing a method for processing defective loop data according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a well-known 4-megabit magnetic bubble memory device, and FIG. FIG. 4 is a circuit diagram showing one block of a magnetic bubble memory device; FIG. 4 is a block diagram showing an apparatus for carrying out the method shown in FIG. 1; and FIG. 5 is a flow chart showing a conventional defective loop data processing method. be. ML(0), MLTI), -..., ML(511
)... Minor loop, 2... Direct peripheral circuit, BL (#0), ■ (Ill), BL (j12)
, BL(13)...boot loop, 10, ltl, #
2. #3...Block, ■...Magnetic bubble memory device, 3...Indirect peripheral circuit, 4...RAM. 5...Host system.

Claims (1)

[Claims] 1. Prepare a plurality of blocks of magnetic bubble memory devices each including a plurality of minor loops and a boot loop for storing which minor loop among the minor loops is defective, and If the access to any one is the first access to the plurality of blocks, the bad loop data is read from all the boot loops of the plurality of blocks and stored in RAM, and then the data on the minor loops of each of the plurality of blocks is read. A method for processing defective loop data in a magnetic bubble memory device, characterized in that: in this case, data from a defective minor loop is not read out based on defective loop data already stored in the RAM.