JPS61102886A - Circuit for multiple-signal sampling - Google Patents

Abstract

PURPOSE:To form easily and acurately a sampling gate for multiple-signal without uisng an integration circuit by providing a comparator to compre count er output and a preset value, and a mean which generates a gate to be made operatable at outputting from a comparator to sample a signal that is super posed during a vertical flyback period. CONSTITUTION:To the reset input of a counter 11, horizontal synchronizing pulses are inputted through a horizontal synchronizing pulse input terminal 2, and the counter 11 is reset at every 1H. To one input of a comparator 12, the output of the counter 11 is supplied, while to the other input, the output of a set value circuit 13 is added. The output of this comparator 12 is supplied to a gate generator drive 14. To one input of a gate generator circuit 6, the output of the gate generator drive circuit 14 is connected, and to the other input is connected with the horizontal synchronizing pulses. From the output of this gate generator 6, via sampling gate output terminal 7, the sampling gate is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a game generation circuit for extracting multiplexed signals transmitted in a vertical blanking period of a television signal.

2. Description of the Related Art Structures and Problems of Conventional Examples For example, teletext is a broadcasting system that transmits image information made up of characters and graphics, such as weather forecasts, news, stock information, etc., using digital data signals.

The character signal is a packet whose unit is one horizontal scanning period.
As shown in Figure 1, during the vertical retrace period of the trap TV signal, the first
In the field, the first o-th horizontal scanning period is from 1oH to 21H, and in the second field, from 273H to 284H.
Multiplex transmission is performed during the period up to H.

FIG. 2 shows the circuit configuration of a conventional example. In the figure, 1 is a composite synchronization signal input terminal, 2 is a horizontal synchronization pulse input terminal, and 3 is a horizontal synchronization pulse input terminal.
4 is an integrating circuit, 4 is a slice circuit, 5 is a slice level setting circuit, 6 is a gate generation circuit, and 7 is a sampling gate output terminal.

In this circuit example, a composite synchronization signal is applied to the integration circuit 3 via the composite synchronization signal input terminal 1 . The output of the integrating circuit 3 is applied to one input of the slicing circuit 4, and the output of the slicing level setting circuit 5 is applied to the other input. The output of the slicing circuit 4 is applied to one input of the gate generation circuit 6, the horizontal synchronization pulse is applied to the other input via the horizontal synchronization pulse input terminal 2, and the sampling gate output is the output of the slice circuit 4. It is obtained via the extraction gate output terminal 7.

FIGS. 3a and 3b show a composite synchronization signal supplied via the composite synchronization signal input terminal 1. FIG.

FIG. 3a shows the case of the first field, and FIG. 3a shows the case of the second field. C in the figure represents a horizontal synchronization pulse synchronized with the horizontal synchronization signal. d and e in the figure show the outputs of the integrating circuit 3 corresponding to the first field and the second field, respectively. The output of this integrating circuit 3 is input to the slicing circuit 4, and when it exceeds a certain slice level set by the slicing level setting circuit 6,
This slice circuit 4 outputs a reference signal, and the gate generation circuit 6 becomes operational. From this point on, the gate generating circuit e starts counting the horizontal synchronizing pulses and generates a sampling gate if.

That is, in this circuit example, a method is used in which a vertical synchronizing signal is detected using an integrating circuit, a detection signal is generated, and horizontal synchronizing pulses are counted.

However, with this method, as shown in Figure 3C, the vertical synchronization signals of the first field and the second field are shifted by o, sH when the horizontal synchronization pulse is used as a reference, and the horizontal synchronization signal of both fields is In order to generate an accurate multiplex signal extraction gate without pulse counting errors, it is necessary to adjust the time constant or slice level of the integrating circuit, and it has been difficult to do so without adjustment due to variations in the parts used.

OBJECTS OF THE INVENTION The present invention was made to solve these problems, and it is an object of the present invention to provide a circuit that easily and accurately generates a multiple signal extraction gate without using an integrating circuit.

Composition of the Invention The present invention, in order to detect a vertical synchronization signal in a composite synchronization signal, samples the composite synchronization signal using a clock signal with a higher frequency than the vertical synchronization signal, and calculates the vertical synchronization pulse width of the vertical synchronization signal. Vertical synchronization signals are detected by counting and digital methods.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIG. In the same figure, 1,
2, 6.7 is similar to that shown in FIG. 2 and rffI. The composite synchronization signal is applied to the input of the level conversion circuit 8 via the composite synchronization input terminal 1, and the level-converted composite synchronization signal is connected to one input of the AND gate circuit 1o. A sampling clock signal output from the sampling clock signal generation circuit 9 is connected to the other input of the AND gate circuit 1o, and the output of the AND gate circuit 1Q is added to the count input of the counter 11. Further, the horizontal synchronizing pulse supplied via the horizontal synchronizing pulse input terminal 2 is added to the reset input of this counter 11, and the counter 11 is reset every 1H.
will be reset. The output of the counter 11 is applied to one input of the comparator 12, the output of the set value circuit 13 is applied to the other input, and the output of this comparator 512 is supplied to the input of the gate generation circuit drive circuit 14. be done. The output of the gate generation circuit drive circuit is connected to one input of the gate generation circuit 6, and the horizontal synchronization pulse is connected to the other input. An extraction gate is obtained via.

a, b, c in FIG. 5 are a, b in FIG. 3.

Similar to C, the first field composite synchronization signal, the second field composite synchronization signal, and the horizontal synchronization pulse are shown, respectively. d shows the output of the comparator 12 during the first field, and e shows the output of the comparator 12 during the second field. Further, f indicates the output of the gate generation circuit driving circuit 14, and q indicates the desired multiplexed signal extraction gate output.

The present embodiment will be described below with reference to the timing chart of FIG.

First, a level-converted composite synchronization signal (for example, TTL
The vertical synchronization pulse width of the vertical synchronization signal is counted by the counter 11.

This counter 11 is reset every 1H by the horizontal synchronization pulse.

Next, the comparator 12 compares the output value of this counter 11 with a preset value, and if the output value of this counter 11 is larger, the vertical synchronization pulse detection signal id,
Output like e. The gate generation circuit drive circuit 14
When it receives the vertical synchronization pulse detection signal twice, it outputs a signal that enables the gate generation circuit 6, as shown in FIG. Note that this gate generation circuit drive circuit 14 can also output a signal that enables the gate generation circuit 6 when it receives the vertical synchronization pulse detection signal once. Further, the gate generation circuit driving circuit 14 enables the gate generation circuit 6 to operate for a slightly longer time than the time during which the gate generation circuit 6 outputs the extracted gate.

When the gate generation circuit 6 becomes operational, it counts the horizontal synchronizing pulses, and in the first field from 10H to 21H during the vertical erase period, from 273H to 284H.
The gate signal at '1 is generated as shown at q. In addition,
In this example, in the next field from 1°H to 21H, the full signal that gates all 12H from 273H to 2s4H1 is output, but of course it is also possible to output a signal that gates a specific horizontal scanning period. It is.

Effects of the Invention According to the present invention, it is possible to provide an accurate multiple signal extraction gate circuit without using an integrating circuit that conventionally required adjustment due to variations in components. Furthermore, since the main part of the circuit is constructed of digital circuits, the circuit of the present invention can easily be integrated into an IC, and its effects are remarkable.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining signals during the vertical retrace period, Fig. 2 is a signal sampling circuit diagram of a conventional example, Fig. 3 is a waveform diagram for explaining the operation of the conventional example, and Fig. 4 is an example of an embodiment of the present invention. The block diagram of the signal sampling circuit shown in FIG. 6 is based on the timing chart for explaining the operation of FIG. 4. 1...Composite synchronization signal input terminal, 2...Horizontal synchronization pulse input terminal, 3...Integrator circuit, 4...
... Slice circuit, 5 ... Slice level setting circuit, 6 ... Gate generation circuit, 7 ... Sampling gate output terminal, 8 ... Level conversion circuit, 9 ...・
...Sampling clock generation circuit, 10...
AND gate circuit, 11... Counter, 12.
... Comparator, 13 ... Set value circuit, 14.
...Gate generation circuit drive circuit.

Claims (1)

[Claims] a sampling clock signal generating means for sampling a vertical synchronization pulse of a vertical synchronization signal in the composite synchronization signal; a counter that is reset by a horizontal synchronization pulse synchronized with a horizontal synchronization signal in the composite synchronization signal and counts the sampling clock signal; The present invention is characterized by comprising a comparator for comparing the output of the counter with a preset value, and means for generating a gate that becomes operable at the time of output of the comparator and extracts the signal superimposed on the vertical retrace period. Multiplex signal extraction circuit.