JPS61102055A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61102055A
JPS61102055A JP59224609A JP22460984A JPS61102055A JP S61102055 A JPS61102055 A JP S61102055A JP 59224609 A JP59224609 A JP 59224609A JP 22460984 A JP22460984 A JP 22460984A JP S61102055 A JPS61102055 A JP S61102055A
Authority
JP
Japan
Prior art keywords
chip
alloy
lead frame
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59224609A
Other languages
Japanese (ja)
Inventor
Kenichi Kaneda
金田　賢一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59224609A priority Critical patent/JPS61102055A/en
Publication of JPS61102055A publication Critical patent/JPS61102055A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
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Abstract

PURPOSE:To obtain a semiconductor device having small power-supply noises by previously forming thick Al-Si or Al-Mg processed films on the surface and back of a connecting region for a Fe-Ni lead frame when an IC chip is fixed to a recessed section shaped to a ceramic substrate and an electrode for the IC chip is connected to the lead frame by using a wire. CONSTITUTION:An IC chip 1 is fastened into a recessed section formed at the central section of the surface of a ceramic substrate 2 through an Au metal lized layer 3, and electrodes shaped to the chip 1 are connected to lead frames 5 consisting of a Fe-Ni alloy extending over the outside of the substrate 2 from the top section of the substrate 2 by employing Al small-gage wires 8. Thick alloy layers 7 composed of Al-1% Si, etc. in thickness of 20mum or more are applied previously onto both the surface and backs of internal lead regions positioned at the top sections of the frames 5 at that time. Consequently, the inductance of the frames is reduced largely. Both the back alloy layers 7 and the top sections of the substrate 2 and both the surface alloy layers 7 and a ceramic cap 6 are connected by using glass 4 having the low melting point.

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特にＩＣチップを搭載する
パッケージ（ＩＣ容器）のリードフレーム構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a lead frame structure of a package (IC container) in which an IC chip is mounted.

ＩＣは近年急速に高密度化・高速化が進められているが
、その反面これらのＩＣは、ＩＣチップ内部の電源ノイ
ズに敏感に反応するようになシ、誤動作を起こしやすく
なっている。一般に扁速回路の場合、配線にのるノイズ
は配線系のインダクタンス成分りによって誘起されるも
のであり、ノイズ量は次式で表わされる。In recent years, ICs have been rapidly becoming denser and faster, but on the other hand, these ICs have become more sensitive to power supply noise within the IC chip and are more likely to malfunction. Generally, in the case of a flat circuit, the noise on the wiring is induced by the inductance component of the wiring system, and the amount of noise is expressed by the following equation.

ΔＶ＝Ｌ（Δｉ／Δｔ）　　　　　（１）ここで、ΔＶ
はノイズ量、Ｌは配縁系のインダクタンス、Δｉは出力
スイッチング時の電流の変化分、Δｔは電流変化時の立
ち上シ及び立ち下シ時間である。上式よシノイズ量は、
配線系の寄生インダクタンスＬに比例する。この寄生的
インターフタンスは様々な要素から成るが、パッケージ
については外部リードと内部リード及びボンディングワ
イヤが関係し、その形状・材質によシインダクタンス値
は変わる。一般に断面形状が矩形で、長さ１の配線に生
ずる自己インダクタンスＬは、で表わされる。ここで、
μは配線材料の透磁率、Ｒは幾何学的平均距離である（
Ｒは配線の断面寸法たてとよとの計算式で示される）。ΔV=L(Δi/Δt) (1) Here, ΔV
is the amount of noise, L is the inductance of the wiring system, Δi is the change in current during output switching, and Δt is the rise and fall times when the current changes. According to the above formula, the amount of noise is
It is proportional to the parasitic inductance L of the wiring system. This parasitic interftance is composed of various elements, but in the case of a package, external leads, internal leads, and bonding wires are involved, and the inductance value changes depending on the shape and material of the package. In general, the self-inductance L that occurs in a wiring having a rectangular cross-sectional shape and a length of 1 is expressed as follows. here,
μ is the magnetic permeability of the wiring material, R is the geometric average distance (
R is shown by the formula for calculating the cross-sectional dimensions of the wiring (height and width).

（１）及び（２）式から、ある配線にのるノイズは、配
線材料の透磁率、配線の長さに比例することがわかる。From equations (1) and (2), it can be seen that noise on a certain wiring is proportional to the magnetic permeability of the wiring material and the length of the wiring.

ところで半導体装置は、サーディツプ型やプラスチック
型のようにＩＣ電極を金属リードフレームによシ外部に
取り出している形態のものが大半を占めている。金属リ
ードフレームは通常、封止ガラスやＩＣチップとの熱膨
張係数のマツチングを取る必要から、鉄−ニッケル合金
たとえば４５合金、４２合金が使われる。これら鉄−ニ
ッケル合金の金属リードフレームを使用した半導体装置
は、フレーム素材が強磁性体のため配線の透磁率が大き
いことが原因で、ＩＣチップにのる電源ノイズ量が大き
いという欠点がある。Incidentally, most semiconductor devices are of the type such as a cerdip type or a plastic type, in which IC electrodes are taken out to the outside through a metal lead frame. Iron-nickel alloys such as 45 alloy and 42 alloy are usually used for the metal lead frame because it is necessary to match the coefficient of thermal expansion with the sealing glass and the IC chip. Semiconductor devices using these iron-nickel alloy metal lead frames have a drawback in that a large amount of power supply noise is applied to the IC chip because the frame material is a ferromagnetic material and the magnetic permeability of the wiring is high.

この欠点の解消策としては、フレーム素材を透磁率の小
さい材料たとえば銅合金リードフレームに変える方法が
ある。しかしこの方法では、熱膨張係数の不適合からサ
ーディツプ型半導体装置では封止ガラスの割れによるパ
ッケージの気密不良、プラスチック型半導体装置ではＩ
Ｃチップの割れによる動作不良の問題が生ずる。また別
の解消策としては、配線の長さを短くする方法があるが
、金属リードフレームの配線形状が非対称になシ、金属
リードフレーム製造時のプレス加工性の悪化、ＩＣ組立
工程の複雑化の問題が生ずる。As a solution to this drawback, there is a method of changing the frame material to a material with low magnetic permeability, such as a copper alloy lead frame. However, with this method, due to the incompatibility of thermal expansion coefficients, cerdip type semiconductor devices have poor sealing of the package due to cracks in the sealing glass, and plastic type semiconductor devices have poor airtightness due to cracks in the sealing glass.
The problem of malfunction due to cracking of the C chip arises. Another solution is to shorten the length of the wiring, but the wiring shape of the metal lead frame becomes asymmetrical, deterioration of press workability when manufacturing the metal lead frame, and complication of the IC assembly process. The problem arises.

本発明の目的は、上記従来技術の問題点を解消した低電
源ノイズの半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with low power supply noise that eliminates the problems of the prior art described above.

本発明の半導体装置は、パッケージの構造改善によシイ
ンダクタンスを低減し低電源ノイズ化を図ったもので、
ＩＣ電極を鉄−ニッケル合金から成るリードフレームに
よシ外部に取り出している半導体装置において、リード
フレームの内部リード領域両面に厚さ２０μ以上のアル
ミニウム合金の加工膜を設けたことを特徴とするもので
ある。The semiconductor device of the present invention is designed to reduce inductance and reduce power supply noise by improving the structure of the package.
A semiconductor device in which IC electrodes are taken out to the outside through a lead frame made of an iron-nickel alloy, characterized in that a processed film of aluminum alloy with a thickness of 20μ or more is provided on both sides of the internal lead area of the lead frame. It is.

以下、本発明をサーディツプ型半導体装置を例にと）説
明する。第１図は、本発明によるサーディツプ型半導体
装置の一実施例を示す図でおる。The present invention will be explained below using a cerdip type semiconductor device as an example. FIG. 1 is a diagram showing an embodiment of a cerdip type semiconductor device according to the present invention.

図において、ＩＣチップ１はセラミック基板２の中央凹
部に金メタライズ層３を介して２固着されている。セラ
ミック基板２には低融点ガラス４によシ厚さ２５０μの
４５合金（Ｆｅ／４５Ｎｉ　）リードフレーム５が固着
されている。この４５合金リードフレーム５の内部リー
ド領域（上２ミックキャップ６に封止され、外から見え
なくなる半導体装置内部のリードブレーム領域）両面に
は、厚さ８０μ（片面８０μ、両面で１６０μ）のアル
ミニウム−１％シリコン合金層７が形成されている。In the figure, an IC chip 1 is fixed to a central recessed portion of a ceramic substrate 2 with a gold metallized layer 3 interposed therebetween. A 45 alloy (Fe/45Ni) lead frame 5 having a thickness of 250 μm is fixed to the ceramic substrate 2 through a low melting point glass 4 . The inner lead area of this 45 alloy lead frame 5 (the lead frame area inside the semiconductor device that is sealed in the upper two Mick caps 6 and becomes invisible from the outside) is made of aluminum with a thickness of 80μ (80μ on one side, 160μ on both sides). -1% silicon alloy layer 7 is formed.

そして、ＩＣチップ１の各電極はアルミニウム細線８に
よシ前記アルミニウムー１％シリコン合金層７に超音波
ポンディング法で結線している。Each electrode of the IC chip 1 is connected to the aluminum-1% silicon alloy layer 7 using a thin aluminum wire 8 by ultrasonic bonding.

アルミニウム−１％シリコン合金層７は、非磁性体のた
め下地の４５合金よ）もはるかに透磁率が低く、シかも
両面で１６０μの厚みを有するので、内部リードのイン
ダクタンスを大幅に引き下げる効果がある。Since the aluminum-1% silicon alloy layer 7 is a non-magnetic material, it has a much lower magnetic permeability than the underlying 45 alloy, and has a thickness of 160μ on both sides, so it has the effect of significantly lowering the inductance of the internal leads. be.

本発明の半導体装置によれば、従来技術に比し内部リー
ドフレームのインダクタンスが大幅に減少するため、大
幅な低電源ノイズ減少を実現できる。According to the semiconductor device of the present invention, since the inductance of the internal lead frame is significantly reduced compared to the conventional technology, it is possible to achieve a significant reduction in power supply noise.

本発明では、図のようにリードフレームの内部リード領
域両面にアルミニウム合金の加工膜を厚く設けているこ
とが新規な点で、従来技術にはなかった点である。加工
膜の厚さは、従来技術ではリードフレーム上面にボンデ
ィングワイヤ接続用として、０．５〜１０μ程度のアル
ミニウム層を設けているが、本発明ではインダクタンス
を低減させるため、２０μ以上形成している。加工膜の
形成は、リードフレーム素材にクラッド法で行えばよい
。The present invention is novel in that a thick processed film of aluminum alloy is provided on both sides of the internal lead region of the lead frame as shown in the figure, which was not found in the prior art. Regarding the thickness of the processed film, in the conventional technology, an aluminum layer of about 0.5 to 10 μm is provided on the top surface of the lead frame for bonding wire connection, but in the present invention, it is formed to a thickness of 20 μm or more in order to reduce inductance. . The processed film may be formed on the lead frame material by a cladding method.

本発明では、加工膜は実施例のアルミニウム−シリコン
合金以外にアルミニウムーマグネシウム合金、アルミニ
ウムーニッケル合金、アルミニウムーマンガン合金、ア
ルミニウムージルコニウム合金、アルミニウムー畑合金
、アルミニウムー銀合金でも同等の効果を発探する。こ
れらの合金は、透磁率が低く、ボンディングワイヤが接
続可能でなければならないので、その組成はいずれもア
ルミニウムを主体とし、第二金属は数百ＰＰＭ〜数多の
添加量でなければならない。加工膜の選定・第二金属の
添加量は、膜厚、ボンディングワイヤの材質に応じて決
める。In the present invention, in addition to the aluminum-silicon alloy used in the example, the processed film can also be used with an aluminum-magnesium alloy, an aluminum-nickel alloy, an aluminum-manganese alloy, an aluminum-zirconium alloy, an aluminum-Hata alloy, and an aluminum-silver alloy. Discover. These alloys must have low magnetic permeability and must be connectable to bonding wires, so their composition must be mainly aluminum, with the second metal added in an amount ranging from several hundred ppm to many. The selection of the processed film and the amount of the second metal added are determined depending on the film thickness and the material of the bonding wire.

なお本発明の半導体装置は実施例のブーディップ型に限
定されるものではなく、プラスチック型も含むことはも
ちろんの事である。It should be noted that the semiconductor device of the present invention is not limited to the boodip type of the embodiment, but also includes a plastic type.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明によるサーディツプ警手導体装置の実
施例を示す。 なお図において、１・・・・・・ＩＣチップ、２・・・
・・・セラミック基板、３・・・・・・金メタライズ層
、４・・・・・・低融点ガラス、５・・・・・・４５合
金リードフレーム、６・・・・・・セラミックキャップ
、７・・・・・・アルミニウム−１％シリコン合金層、
８・・・・・・アルミニウム細綜である。 一′、、、　、ｓ 代理人　弁理士　　内　原　　　３．　　。 第１図FIG. 1 shows an embodiment of a cerdip guard conductor device according to the present invention. In the figure, 1...IC chip, 2...
... Ceramic substrate, 3 ... Gold metallized layer, 4 ... Low melting point glass, 5 ... 45 alloy lead frame, 6 ... Ceramic cap, 7... Aluminum-1% silicon alloy layer,
8...It is an aluminum skein. 1'、、、、s Agent Patent Attorney Uchihara 3. . Figure 1

Claims (3)

【特許請求の範囲】[Claims] （１）ＩＣ電極を鉄−ニッケル合金から成るリードフレ
ームにより外部に取り出している半導体装置において、
リードフレームの内部リード領域両面に厚さ２０μ以上
のアルミニウム合金の加工膜を設けたことを特徴とする
半導体装置。(1) In a semiconductor device in which an IC electrode is taken out to the outside through a lead frame made of an iron-nickel alloy,
A semiconductor device characterized in that a processed film of aluminum alloy with a thickness of 20 μm or more is provided on both sides of an internal lead region of a lead frame. （２）アルミニウム合金は、アルミニウム−シリコン合
金から成る特許請求範囲第（１）項記載の半導体装置。(2) The semiconductor device according to claim (1), wherein the aluminum alloy is an aluminum-silicon alloy. （３）アルミニウム合金は、アルミニウム−マグネシウ
ム合金から成る特許請求範囲第（１）項記載の半導体装
置。(3) The semiconductor device according to claim (1), wherein the aluminum alloy is an aluminum-magnesium alloy.
JP59224609A 1984-10-25 1984-10-25 Semiconductor device Pending JPS61102055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59224609A JPS61102055A (en) 1984-10-25 1984-10-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59224609A JPS61102055A (en) 1984-10-25 1984-10-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61102055A true JPS61102055A (en) 1986-05-20

Family

ID=16816403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59224609A Pending JPS61102055A (en) 1984-10-25 1984-10-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61102055A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0425691A1 (en) * 1989-05-01 1991-05-08 Sumitomo Electric Industries, Ltd. Lead frame for semiconductor devices
JPH04133456A (en) * 1990-09-26 1992-05-07 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0425691A1 (en) * 1989-05-01 1991-05-08 Sumitomo Electric Industries, Ltd. Lead frame for semiconductor devices
JPH04133456A (en) * 1990-09-26 1992-05-07 Nec Corp Semiconductor device

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