JPS61101867A - 二重化プロセツサにおける割込み制御方式 - Google Patents

二重化プロセツサにおける割込み制御方式

Info

Publication number
JPS61101867A
JPS61101867A JP22324484A JP22324484A JPS61101867A JP S61101867 A JPS61101867 A JP S61101867A JP 22324484 A JP22324484 A JP 22324484A JP 22324484 A JP22324484 A JP 22324484A JP S61101867 A JPS61101867 A JP S61101867A
Authority
JP
Japan
Prior art keywords
processor
interrupt
processors
levels
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22324484A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0149981B2 (enrdf_load_stackoverflow
Inventor
Noboru Ita
板　昇
Shigeru Mitsugi
身次　茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP22324484A priority Critical patent/JPS61101867A/ja
Publication of JPS61101867A publication Critical patent/JPS61101867A/ja
Publication of JPH0149981B2 publication Critical patent/JPH0149981B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP22324484A 1984-10-24 1984-10-24 二重化プロセツサにおける割込み制御方式 Granted JPS61101867A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22324484A JPS61101867A (ja) 1984-10-24 1984-10-24 二重化プロセツサにおける割込み制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22324484A JPS61101867A (ja) 1984-10-24 1984-10-24 二重化プロセツサにおける割込み制御方式

Publications (2)

Publication Number Publication Date
JPS61101867A true JPS61101867A (ja) 1986-05-20
JPH0149981B2 JPH0149981B2 (enrdf_load_stackoverflow) 1989-10-26

Family

ID=16795052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22324484A Granted JPS61101867A (ja) 1984-10-24 1984-10-24 二重化プロセツサにおける割込み制御方式

Country Status (1)

Country Link
JP (1) JPS61101867A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0149981B2 (enrdf_load_stackoverflow) 1989-10-26

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