JPS6098648A - Chip carrier for flip chip - Google Patents

Abstract

PURPOSE:To contrive to improve the reliability by improvement of the degree of adjacency of conductor wiring by a method wherein the wiring of bump electrodes with outer terminal electrodes is performed alternately on the front and back surfaces of the titled carrier. CONSTITUTION:An aperture 15 is previously formed in the chip carrier 11 by corresponding to a flip chip, and the pattern of conductor wirings 16 which draw conductors from the bump electrodes 12 via aperture to the back of the chip carrier is formed. This manner enables the connection of the bump electrodes to the outer terminal electrodes 13. When the wiring of connecting the electrodes 12 and 13 on the surface as normal and the wiring from the electrodes 12 to the back via wiring conductors 16 and aperture 15 are performed alternatlely, the degree of adjacency of wiring conductors 14 is largely improved, and the reliability becomes much higher.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a chip carrier, particularly a chip carrier for a 7-rib chip.

[Prior art]

Chip carriers are generally semiconductor device Kedaibond,
The carrier 1C is assembled by wire bonding, but due to its ease of assembly and the increasing number of connection points, flip-chip applications are also being considered.

Since flip chips have solder electrodes called bumps, they are widely used because they can be assembled together with other active and passive components on a hybrid circuit board through solder reflow. However, as semiconductor devices become more complex and denser (and the spacing between bumps becomes narrower), in addition, when trying to check out the full pressure of the electrical and physical characteristics of semiconductor devices, hybrid circuit boards On the contrary, inconvenient situations may occur if other parts are assembled separately.For this reason, a method is adopted in which only non-defective products are assembled into a t-hybrid circuit board after sub-assembly as in the Chimp Carry 7 method.

When assembling into a chip carrier, the assembly yield decreases when the number of bumps is large and the spacing between bumps becomes narrow.In addition, the spacing between the conductor wiring from the bump electrode to the external terminal electrode of the chip carrier is also narrow. Bridges and metal migration are likely to occur.

That is, FIG. 1 is a perspective view of a conventional chimbu carrier for 7 lift chips. On the chip carrier 1, there are bump electrodes 2 corresponding to the bumps of the 7 lip chips. External terminal electrode 3
．． A wiring conductor 4 connecting these bump electrodes 2 and external terminal electrodes 3 is formed. In order to manufacture this balance carrier 1'11f at low cost, a method of printing and firing electrode metal similar to that of the thick film substrate is used. However, as the number of bump electrodes 2 increases and the spacing between the bumps narrows, the spacing between the wiring conductors 4 also becomes quite close, which tends to cause bridging between conductors and migration between wiring metals. As a countermeasure to this problem, there is a multilayer ceramic chip carrier system, but it is expensive and has problems in practical use.

[Summary of the invention]

This invention was invented in view of the above points, and is a flip chip in which the degree of adjacency of conductor wiring is improved by alternately performing conductor wiring between bump electrodes and external terminal electrodes on the front and back sides of the butt carrier. The present invention provides chip carriers for

[Embodiments of the invention]

FIG. 2 is a perspective view showing an embodiment of the present invention. 11
is a chip carrier, and this chip carrier 11 has a bump electrode, a pole 12 and an external terminal 1! A pole 13 is formed. 14 is a wiring conductor, and in this invention, this wiring conductor 14
are always placed without adjacency. In other words, the chip carrier 1 is prepared in advance in correspondence with the frimb chip.
An opening 15 is formed on the bump electrode 12, and a pattern of conductive wiring 16 is formed so as to draw a conductor from the bump electrode 12 to the back surface of the chip carrier 11 through the opening 15'. and connection 7 to external terminal electrodes 13.

51C, since the number of bumps is large and the spacing between the bumps is narrow, if the wiring conductors 14 are extremely adjacent to each other, the connection to the bump electrode 12 and external terminal electrode 13 should be wired on the surface as usual; If the bumps are alternately formed with the wiring conductors 16 from the poles 12 to the back surface and the wiring through the 15% opening, the degree of adjacency of the wiring conductors 14 is greatly improved and the reliability is further improved.

In addition, unlike multilayer ceramic systems, the cost does not increase much compared to conventional methods, and it can be manufactured at low cost using the conventional Solses manufacturing method for single-phase chip carriers.

〔Effect of the invention〕

As explained above, this invention forms an opening Y in the center of a chip carrier, and supports a plurality of bump electrodes provided around this opening and the bump electrodes provided on the outer periphery of the chip carrier. When connecting external terminal electrodes and T-conductor wiring, the wiring is arranged alternately on the front and back sides of the chip carrier, so the degree of adjacency between the conductor wiring is thick (although it will be improved, it is a highly reliable flip-chip device. There is an advantage that a chip carrier can be obtained.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing a conventional chip carrier, and FIG. 2 is a perspective view of a chip carrier showing an embodiment of the present invention. In the figure, 11 is a chip carrier, 12i1 bump electrode, 1
3 is an external terminal electrode, 14 is a wiring conductor, 15 is an opening, 1
6 is a conductor wiring. 371 Director General 1. Indication of the case: Japanese Patent Application No. 5E-2OEAEO No. 2, title of invention: Chip carrier for flip chip; 3. Relationship with the case of the person making the amendment Patent applicant address Chiyo, Tokyo [11-ku 90-2 I' I I 2
a: 3 Y;・Name (601) E, Ryodenki Co., Ltd. Representative Kata 111 Jin Hachibe 4, Agent Address Marunouchi-X°Tai 112 City, T. Dai III Ward, Tokyo; 3 No. 5; Claims column 1 of the specification to be amended; Detailed explanation of the invention;
and a brief explanation of the drawings 6, Contents of amendment (1) The scope of false claims in 4□1r of the specification is amended as shown in the attached sheet. (2) Specification page 2, line 16, page 3, lines 16 and 18, t
54 pages 10 q-1, page 5 lines 9 and 11 r > 14
．． All of the conductive lines J are referred to as "conductor lines". (3) Similarly, “16 is conductor wiring” on page 55, line 20,
Complement 1 with "16 is a wiring conductor." 2. An opening 1-1 is formed in the center of the chip carrier, and a plurality of bump electrodes formed around the opening and an outer periphery of the chip carrier are formed in the center of the chip carrier. An external terminal electrode provided corresponding to the bump electrode formed on the chip carrier is connected to the front surface of the chip carrier and the back surface of the chip carrier through the opening by wiring conductors. Flip chip river chip carrier.

Claims (1)

[Claims] An opening corresponding to a seven-layer chip is formed in the center of the chip carrier, and a plurality of bumps formed around the opening correspond to the first bump electrode formed on the outer periphery of the chip carrier. 1. A chimp carrier for flimp chimps, characterized in that external terminal electrodes provided on the chip carrier are alternately connected to the surface of the chip carrier and the nose surface of the chip carrier through the opening by conductive wiring.