JPS609667B2 - Semiconductor controlled rectifier - Google Patents

Semiconductor controlled rectifier

Info

Publication number
JPS609667B2
JPS609667B2 JP52040418A JP4041877A JPS609667B2 JP S609667 B2 JPS609667 B2 JP S609667B2 JP 52040418 A JP52040418 A JP 52040418A JP 4041877 A JP4041877 A JP 4041877A JP S609667 B2 JPS609667 B2 JP S609667B2
Authority
JP
Japan
Prior art keywords
region
electrode
layer
controlled rectifier
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52040418A
Other languages
Japanese (ja)
Other versions
JPS53126283A (en
Inventor
南 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP52040418A priority Critical patent/JPS609667B2/en
Publication of JPS53126283A publication Critical patent/JPS53126283A/en
Publication of JPS609667B2 publication Critical patent/JPS609667B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839Cathode regions of thyristors

Description

【発明の詳細な説明】 本発明は半導体制御整流装置に関するもので、その目的
とするものは小制御電流で点弧し得るとともにdv/d
t耐量の向上を図ることにある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor-controlled rectifier device, which aims to be capable of ignition with a small control current and to reduce dv/d.
The objective is to improve the t tolerance.

一般に制御電極によって点弧される半導体制御整流装置
(以下サィリスタと云う)はpnpnの4層接合構造を
有する半導体基体と、この半導体基体の両外側のp層お
よびn層上にそれぞれ設けられた2個の電極と、中間の
p層あるいはn層のどちらか一方に接続した制御電極を
具備している。たとえば第1図に示すような構造のもの
に高いdv/dtを印加した場合、その変位電流はP2
層からカソード電極1へ矢印のように流れるが、周辺の
&層の下のp2層を通りカソード電極1へと流れる。周
辺の山層の下のp2層を通る電流は−層周辺の露出した
p2層を流れる全電流であるため、第1図Bに示すp2
層の横方向電圧降下V^Bが高くなり、サィリスタを点
弧させるに十分な値となりうる。そのためdv/dt耐
量が低い。一方初期点弧特性を改良するために種々の制
御電極構造が提案されている。その1例を第2図に示す
。ゲート電極11とェミッタ層12間に補助サイリス夕
のェミツタ層13を設けたいわゆるパイロットゲート構
造のサィリスタであって、補助サィリスタ電極14がp
ベース層15にェミッタ層12と対向して設けられてい
る。
Generally, a semiconductor controlled rectifier (hereinafter referred to as a thyristor) which is ignited by a control electrode has a semiconductor substrate having a pnpn four-layer junction structure, and two thyristors provided on the p-layer and n-layer on both sides of the semiconductor substrate. The control electrode is connected to either the intermediate p layer or the n layer. For example, when a high dv/dt is applied to the structure shown in Figure 1, the displacement current is P2
It flows from the layer to the cathode electrode 1 as shown by the arrow, but it also flows to the cathode electrode 1 through the p2 layer below the surrounding & layer. The current passing through the p2 layer under the surrounding mountain layer is the total current flowing through the exposed p2 layer around the − layer, so the p2 shown in Figure 1B is
The lateral voltage drop V^B across the layer becomes high and can be of sufficient value to fire the thyristor. Therefore, the dv/dt tolerance is low. On the other hand, various control electrode structures have been proposed to improve the initial ignition characteristics. An example is shown in FIG. The thyristor has a so-called pilot gate structure in which an emitter layer 13 of an auxiliary thyristor layer is provided between a gate electrode 11 and an emitter layer 12, and the auxiliary thyristor electrode 14 is p
It is provided on the base layer 15 so as to face the emitter layer 12 .

このものではェミッタ電極16と補助サィリスタ電極1
4の対向部分の対向距離を長くすることによって初期点
弧面積を改良することができる。すなわち補助サィリス
タ電極と対向するェミッタ電極16はェミツタ層12端
部表面が露出するように形成されていて、補助サイリス
タ電極より流入するゲート電流がェミッタ層端部のpn
接合に流入し、ゲート電流が有効にはたらくようになっ
ている。第3図によりこのようなサィリスタにおける変
位電流による電圧降下をみる。
In this one, the emitter electrode 16 and the auxiliary thyristor electrode 1
The initial ignition area can be improved by increasing the distance between the opposing portions of No. 4. That is, the emitter electrode 16 facing the auxiliary thyristor electrode is formed so that the surface of the end of the emitter layer 12 is exposed, and the gate current flowing from the auxiliary thyristor electrode flows into the pn of the end of the emitter layer.
The gate current flows into the junction and becomes effective. The voltage drop caused by the displacement current in such a thyristor is seen in FIG.

第3図Aはェミッタ層端部近傍とェミツタ層端部に対向
するゲート電流の一部分を示し、第3図Bは第3図Aの
B−B断面図を示すものである。ェミッタ層12の外側
で発生した変位電流がェミッタ層端部に一番近い短絡ヱ
ミッタ孔201こ矢印のように流れ込むとすると、第3
図Bのab間の電圧降下は次の式であらわされる。すな
わち周辺近傍の短絡ェミッ夕が規則に配置されていると
して、その単位部分における変位電流による電圧降下を
計算すると、Vabら′昼JSp台芸コp‐JSI賀こ
こに方はpベース層の平均抵抗 Jは変位電流密度 S凶=3xlo‐2(地) ※Sは変位電流の発生する周辺p層の面積J=C祭 s宅=D‐濃b=1。
3A shows a portion of the gate current near the end of the emitter layer and facing the end of the emitter layer, and FIG. 3B shows a sectional view taken along line BB in FIG. 3A. Assuming that the displacement current generated outside the emitter layer 12 flows into the short-circuit emitter hole 201 closest to the end of the emitter layer as shown by the arrow, the third
The voltage drop between a and b in Figure B is expressed by the following equation. In other words, assuming that the short-circuit emitters near the periphery are arranged regularly, and calculating the voltage drop due to the displacement current in the unit part, we can calculate the voltage drop due to the displacement current in the unit part. Resistance J is the displacement current density S = 3xlo-2 (ground) *S is the area of the surrounding p layer where the displacement current occurs J = C = D - density = 1.

‐lab普通のサィリス夕ではn+層の下のp層の値と
してはで;1ぴ〜1ぴ(Q)、またCこ800PE/の
(Vら0にて)であるので、J:8×1o−・0群(A
′の)、 周辺部の寸法として少なくともlo=3肌、lab=1
側は必要であるので、‐・‐Vab=(1ぴ〜帆×(8
×1o−10〉X(3×・o‐2〉沫=2‐4(・o−
この電圧降下によってpn接合が電荷の注入をおこさせ
ないためにはpn接合のしきし、値以下であることが必
要である。
-lab In the case of a normal silicate layer, the value of the p layer below the n+ layer is 1 p to 1 p (Q), and since C is 800 PE/(at V et 0), J: 8× 1o-・0 group (A
), the peripheral dimensions are at least lo = 3 skin, lab = 1
Since the side is necessary, -・-Vab=(1pi~sail×(8
×1o-10〉X(3×・o-2〉=2-4(・o-
In order to prevent the pn junction from injecting charge due to this voltage drop, it is necessary that the voltage is below the threshold value of the pn junction.

pn接合のしきし、値は一般的に知られているように0
.5Vであるから2‐4(lo−3〜10‐9)群=o
‐5したがつて 群:2‐o8×・ぴ〜2‐o8×1び〈V′Sec〉=
(200〜20〉(VルS〉宏耐量ま2o〜2ooV/
〃S‘こ分布するこ比なる。
As is generally known, the threshold value of a pn junction is 0.
.. Since it is 5V, 2-4 (lo-3 to 10-9) group = o
-5 Therefore group: 2-o8×・pi~2-o8×1 and <V′Sec>=
(200~20〉(VruS〉Hiroshi Tolerance 2o~2ooV/
〃S' distribution is the ratio.

本発明‘ま上記地もさらに群耐量を向上させたサィリス
タを提供するものであって、ゲート電極に対向するェミ
ッタ層端部の短絡構造を改良してその目的を蓮せしめる
ものである。
The object of the present invention is to provide a thyristor with further improved group withstand capability, and to achieve the object by improving the short-circuit structure at the end of the emitter layer facing the gate electrode.

以下図面を参照して本発明を説明する。The present invention will be explained below with reference to the drawings.

第4図Aは本発明サィリスタの一部の上面図を示し、第
4図Bは第4図AのB−B線に沿った断面図を示す。第
4図から明らかなように本発明のサィリスタは次の構造
となっている。すなわち導電型がnなる第1領域21、
この第1領域の両主面に隣接した導電型がpなる第2お
よび第3領域22,23、上言己第3領域(ベース層)
表面に一部を露出しかつこの領域内に形成された導電型
がnの第4領域(ェミッタ層)24、上記第2および第
4領域の表面にそれぞれ設けられた第1電極(アノード
電極)25と第2電極(カノード電極)26、上記第3
領域の表面に第2電極を囲続離隔して設けられた第3電
極(補助ゲート電極)27、上記第3領域の表面に上記
第3電極27に対し第4領域と反対側に設けられたゲー
ト電極28、上記第3電極27の下の第3領域内におい
て表面に一部を露出しゲート電極と第4領域との間にそ
れぞれ離隔して形成された導電型がnの第5領域29を
備える。上記の構造のサィリス夕において、第4領域(
ェミッタ層)24のゲート電極に対向する側の端面が第
4図に示すように凹凸状に形成されていて、したがって
このェミッ夕層上に設けられた第2電極であるアルミニ
ウムを蒸着させて形成されたカソード電極が上記ヱミッ
タ層の凹部を覆い、pベース層とnェミツタ層とが短絡
された構造となつている。
FIG. 4A shows a top view of a part of the thyristor of the present invention, and FIG. 4B shows a sectional view taken along the line BB in FIG. 4A. As is clear from FIG. 4, the thyristor of the present invention has the following structure. That is, the first region 21 whose conductivity type is n,
The second and third regions 22 and 23, which are adjacent to both main surfaces of the first region and have a p conductivity type, the third region (base layer).
A fourth region (emitter layer) 24 of conductivity type n which is partially exposed on the surface and formed within this region, and a first electrode (anode electrode) provided on the surfaces of the second and fourth regions, respectively. 25, a second electrode (canodic electrode) 26, and the third electrode
A third electrode (auxiliary gate electrode) 27 is provided on the surface of the region to surround the second electrode and spaced apart from the second electrode, and a third electrode (auxiliary gate electrode) 27 is provided on the surface of the third region on the opposite side of the fourth region to the third electrode 27. A fifth region 29 of n conductivity type is formed in a third region under the gate electrode 28 and the third electrode 27 and is partially exposed on the surface and spaced apart between the gate electrode and the fourth region. Equipped with. In the syringe with the above structure, the fourth region (
The end surface of the emitter layer 24 on the side facing the gate electrode is formed in an uneven shape as shown in FIG. The resulting cathode electrode covers the recessed portion of the emitter layer, and the p base layer and n emitter layer are short-circuited.

したがって変位電流は従来のものとは異なり、ェミッタ
層端部の短絡部分に流れ込むことになる。
Therefore, unlike the conventional case, the displacement current flows into the short-circuited portion at the end of the emitter layer.

このときの変位電流によるゲートカソード間の電圧降下
をみると、上記したと同じように単位部分において計算
するとVCd:FCd.J.s・豊=pCdル,Cdこ
こにpはpベース層の周辺部単位部分の平均抵抗であっ
て、通常のサイリスタでは±=7xlo‐2〜1.7x
lo‐1の範囲こ分布してし、P
※る。
Looking at the voltage drop between the gate and cathode due to the displacement current at this time, when calculated for the unit part in the same way as above, VCd:FCd. J. s・Yutaka=pCd le, Cd where p is the average resistance of the peripheral unit part of the p base layer, and in a normal thyristor, it is ±=7xlo-2~1.7x
It is distributed in the range of lo-1, and P
※Ru.

.・.で;6〜15(0) また J=C群、1。..・.. So; 6-15 (0) Also J=C group, 1.

‐ICd:3×10−2ここにloはべレット端部とェ
ミッタ層端部間の距離、lcdはェミッタ層端部とェミ
ッタ層織部に最も近い短絡ヱミッタ部間の距離。
-ICd: 3 x 10-2 where lo is the distance between the end of the pellet and the end of the emitter layer, and lcd is the distance between the end of the emitter layer and the shorted emitter part closest to the emitter layer weave.

したがって前述の計算式のときと同じように、pn接合
のしきし、値が0.5Vであることからして、o‐5=
VCd=(6〜15)X(8×10−10)X(3刈‐
2)X群‐‐祭=6‐94×・ぴ〜2‐78×1■′S
ec=6‐94×1ぴ〜2‐78×1冊ルSとなる。
Therefore, as in the calculation formula above, since the pn junction threshold value is 0.5V, o-5=
VCd=(6~15)X(8×10-10)X(3-
2) Group X--Festival=6-94×・Pi~2-78×1■'S
ec = 6-94 x 1 pi ~ 2-78 x 1 book S.

すなわち群耐量側ooVル沙ら25ooVルS側囲に分
布することになる。
In other words, it is distributed between the group tolerance side ooV Lusa and 25ooV Le S side.

このよう端低下をもたらす素子周辺の変位電流は各短絡
部分に均等に分割されて、そのほとんどがベース領域か
らカソード電極へ向って流れることになる。
The displacement current around the element that causes such an edge drop is equally divided into each short-circuited portion, and most of it flows from the base region toward the cathode electrode.

したがって本発明のものは大幅に諭量力洞上する。また
上記のような構造のサィリスタにおいて、n導電型の第
5領域のゲート側の端面を凹凸状に形成すれば群耐量独
批向上させるこめできる。
Therefore, the present invention is significantly superior in terms of performance. Furthermore, in the thyristor having the above structure, if the end face of the n-conductivity type fifth region on the gate side is formed into an uneven shape, the group withstand capability can be independently improved.

前述した構造と異なり、たとえばゲート電極が中心とな
りそのまわりもこカソード電極が形成されるなど第5図
に示すようなものなど種々の構造のサィリスタに対して
も、前述の電極あるいはェミツタ層の端面を凹凸形状に
する構造を適用すれば群耐量を向上触るとし、例黙示す
ことは云うまでもない。
Unlike the structure described above, thyristors with various structures, such as the one shown in FIG. It goes without saying that it is implied that if a structure having an uneven shape is applied, the group resistance will be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体制御整流装置の断面図、第2図は
同じく断面図、第3図は従来の半導体制御整流装置の一
部のAは平面図にして、BはAのB−B線にて切断した
断面図、第4図は本発明の一実施例の一部のAは平面図
、BはAのB−B線にて切断した断面図、第5図は本発
明の他の実施例の一部を示す平面図である。 21・・・・・・・・・n型第1領域、22・・・・・
・p型第2領域、23・・・・・・p型第3領域、24
・・・・・・n型第4領域、25・・・・・・第1の電
極、26・・・・・・第2の電極、27・・・・・・第
3の電極、28・・・・・・ゲート電極、29・・・・
・・第5領域。 第1鞠 第2図 第3図 籍4図 第5図
Fig. 1 is a sectional view of a conventional semiconductor-controlled rectifier, Fig. 2 is a sectional view of the same, and Fig. 3 is a plan view of a part of the conventional semiconductor-controlled rectifier, and B is a B-B of A. 4 is a plan view of a part of one embodiment of the present invention, B is a sectional view taken along line B-B of A, and FIG. FIG. 2 is a plan view showing a part of the embodiment. 21......n-type first region, 22...
・P-type second region, 23...p-type third region, 24
. . . N-type fourth region, 25 . . . first electrode, 26 . . . second electrode, 27 . . . third electrode, 28. ...Gate electrode, 29...
...Fifth area. 1st ball, 2nd figure, 3rd book, 4th figure, 5th figure

Claims (1)

【特許請求の範囲】[Claims] 1 第1の導電型の第1領域と、この第1領域の両主面
に隣接して形成された第2の導電型の第2および第3領
域と、上記第3領域の表面に1部を露出しかつ第3領域
内に形成された第1の導電型の第4領域と、上記第2お
よび第4領域の表面にそれぞれ設けられた第1および第
2の電極と、上記第3領域の表面に第2の電極と離隔し
て設けられた制御電極と、上記第3領域内に第4領域と
離隔して制御電極側に形成された第1の導電型の第5領
域と、上記第3および第5領域の表面に第2電極および
制御電極間にそれぞれと離隔し、且つ第4領域を実質的
に囲繞するように設けられた第3の電極とを具備した半
導体制御整流装置において、上記第4領域の第3の電極
側の端面が凹凸状に形成され、その複数の凹部において
第3領域と第4領域とを短絡したことを特徴とする半導
体制御整流装置。
1 A first region of a first conductivity type, second and third regions of a second conductivity type formed adjacent to both main surfaces of the first region, and a portion of the surface of the third region. a fourth region of the first conductivity type exposed and formed in the third region; first and second electrodes provided on the surfaces of the second and fourth regions, respectively; and the third region. a control electrode provided on the surface of the electrode separated from the second electrode; a fifth region of the first conductivity type formed in the third region on the control electrode side and separated from the fourth region; In a semiconductor controlled rectifier device comprising: a third electrode provided on surfaces of the third and fifth regions to be spaced apart from each other between the second electrode and the control electrode and substantially surrounding the fourth region; A semiconductor-controlled rectifier device, characterized in that the end face of the fourth region on the third electrode side is formed in an uneven shape, and the third region and the fourth region are short-circuited at the plurality of concave portions.
JP52040418A 1977-04-11 1977-04-11 Semiconductor controlled rectifier Expired JPS609667B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52040418A JPS609667B2 (en) 1977-04-11 1977-04-11 Semiconductor controlled rectifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52040418A JPS609667B2 (en) 1977-04-11 1977-04-11 Semiconductor controlled rectifier

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP11841382A Division JPS608633B2 (en) 1982-07-09 1982-07-09 Semiconductor controlled rectifier

Publications (2)

Publication Number Publication Date
JPS53126283A JPS53126283A (en) 1978-11-04
JPS609667B2 true JPS609667B2 (en) 1985-03-12

Family

ID=12580102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52040418A Expired JPS609667B2 (en) 1977-04-11 1977-04-11 Semiconductor controlled rectifier

Country Status (1)

Country Link
JP (1) JPS609667B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2150347B (en) * 1983-11-21 1987-02-25 Westinghouse Brake & Signal Amplifying gate thyristor with zones of different cathode-gate resistance
DE3917100A1 (en) * 1989-05-26 1990-11-29 Eupec Gmbh & Co Kg THYRISTOR

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS441024Y1 (en) * 1966-04-13 1969-01-16
JPS5022400A (en) * 1973-06-29 1975-03-10

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS441024Y1 (en) * 1966-04-13 1969-01-16
JPS5022400A (en) * 1973-06-29 1975-03-10

Also Published As

Publication number Publication date
JPS53126283A (en) 1978-11-04

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