JPS6095659U - computing device - Google Patents

computing device

Info

Publication number
JPS6095659U
JPS6095659U JP18664483U JP18664483U JPS6095659U JP S6095659 U JPS6095659 U JP S6095659U JP 18664483 U JP18664483 U JP 18664483U JP 18664483 U JP18664483 U JP 18664483U JP S6095659 U JPS6095659 U JP S6095659U
Authority
JP
Japan
Prior art keywords
input terminal
inverting input
voltage
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18664483U
Other languages
Japanese (ja)
Other versions
JPS6142191Y2 (en
Inventor
南 博志
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP18664483U priority Critical patent/JPS6095659U/en
Publication of JPS6095659U publication Critical patent/JPS6095659U/en
Application granted granted Critical
Publication of JPS6142191Y2 publication Critical patent/JPS6142191Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の演算装置の実施例を示すブロック図、゛
第2図は第1図の絶対値回路と極性検出回路の具体的な
実施例を示すブロック図、第3図は極性の切り換りの不
安定性に一因する出力の変動を示す説明図、第4図は本
考案の要部の実施例を示すブロック図、第5図は第4図
において直流電流信号に対する比較器の各入力電圧の変
化を示す説明図、第6図は第4図において直流電流信号
に対する比較器の両入力端の電位差の変化を示す説明図
である。 1・・・入力端、2・・・絶対値回路、3・・・演算回
路、4・・・乗算回路、5・・・極性検出回路、6〜9
・・・出力端、Q工・・・演算増幅器、Q3・・・比較
器、Dl、D2・・・ダ。 イオード、■・・・直流電流信号。
Figure 1 is a block diagram showing an example of a conventional arithmetic unit, Figure 2 is a block diagram showing a specific example of the absolute value circuit and polarity detection circuit in Figure 1, and Figure 3 is a block diagram showing a specific example of the absolute value circuit and polarity detection circuit in Figure 1. FIG. 4 is a block diagram showing an embodiment of the main part of the present invention. FIG. FIG. 6 is an explanatory diagram showing changes in the input voltage. FIG. 6 is an explanatory diagram showing changes in the potential difference between both input ends of the comparator with respect to the DC current signal in FIG. 4. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Absolute value circuit, 3... Arithmetic circuit, 4... Multiplication circuit, 5... Polarity detection circuit, 6-9
...output end, Q component...operational amplifier, Q3...comparator, Dl, D2...da. Iode, ■...DC current signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 正風負両極性に反転する直流電流信号が与えられる入力
端と演算増幅器の反転入力端および非反転入力端との間
に互いに逆極性に接続された1対のダイオードと、前記
演算増幅器の出力端と前記反転入力端との間ピ接続され
た抵抗と、前記非反転入力端と共通、電位点との間に接
続された抵抗、と、前記出力端の絶対値電圧に関連した
電圧と前記非反転入力端の電圧とを比較する比較器とを
具−備し、前記出力端に得られた絶対値電圧を単一極性
のスイッチを含む演算回路を介して得た電圧と前記比較
的の出力とから前記直流電流信号の極性に対応した極性
の電圧出力を得る演算装置。
a pair of diodes connected with mutually opposite polarities between an input terminal to which a direct current signal inverted to positive and negative polarities is applied, and an inverting input terminal and a non-inverting input terminal of an operational amplifier; and an output terminal of the operational amplifier. and the inverting input terminal, a resistor connected between the non-inverting input terminal and a common potential point, and a voltage related to the absolute value voltage of the output terminal and the non-inverting input terminal; and a comparator for comparing the voltage at the inverting input terminal, and the absolute value voltage obtained at the output terminal is compared with the voltage obtained through the arithmetic circuit including a single-polarity switch and the comparative output. and an arithmetic device that obtains a voltage output with a polarity corresponding to the polarity of the DC current signal.
JP18664483U 1983-12-02 1983-12-02 computing device Granted JPS6095659U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18664483U JPS6095659U (en) 1983-12-02 1983-12-02 computing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18664483U JPS6095659U (en) 1983-12-02 1983-12-02 computing device

Publications (2)

Publication Number Publication Date
JPS6095659U true JPS6095659U (en) 1985-06-29
JPS6142191Y2 JPS6142191Y2 (en) 1986-12-01

Family

ID=30403095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18664483U Granted JPS6095659U (en) 1983-12-02 1983-12-02 computing device

Country Status (1)

Country Link
JP (1) JPS6095659U (en)

Also Published As

Publication number Publication date
JPS6142191Y2 (en) 1986-12-01

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