JPS59160363U

JPS59160363U - Absolute value calculation circuit

Info

Publication number: JPS59160363U
Application number: JP1983055574U
Authority: JP
Inventors: 正男田中
Original assignee: 富士電機株式会社
Priority date: 1983-04-14
Filing date: 1983-04-14
Publication date: 1984-10-27

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の絶対値演算回路の回路図であつ□て、第
２図は第１図の回路の特性図である。第３図は本考案の
一実施例を示す回路図で、第４図は第３図の回路の特性
図、第５図は本考案の別の実施例を示す回路図であ−る
。１・・・・・・直流速度検出発電機、２・・・・・・直
列抵抗、３・・・・・・可変抵抗、５．　６．　７・・
・・・・絶対値演算回路、１０・・・・・・第１演算増
幅器、１１．　１３．　２１゜２２．２４．２５．３１
・・・・・・入力抵抗、・１２゜１４、　２３．　２６
．　３２・・・・・・帰還抵抗、１７・・・・・・並列
ダイオード、１８・・・・・・直列ダイオード、２０・
・・・・・第２演算増幅器、３０・・・・・・第３演算
増幅器、３５・・・・・・第１ダイオード、３６・・・
・・・第２ダイオ−−ド。FIG. 1 is a circuit diagram of a conventional absolute value calculation circuit, and FIG. 2 is a characteristic diagram of the circuit shown in FIG. FIG. 3 is a circuit diagram showing one embodiment of the present invention, FIG. 4 is a characteristic diagram of the circuit of FIG. 3, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. 1...DC speed detection generator, 2...Series resistance, 3...Variable resistance, 5. 6. 7...
. . . Absolute value calculation circuit, 10 . . . First operational amplifier, 11. 13. 21゜22.24.25.31
...Input resistance, ・12゜14, 23. 26
．． 32... Feedback resistor, 17... Parallel diode, 18... Series diode, 20...
...Second operational amplifier, 30...Third operational amplifier, 35...First diode, 36...
...Second diode.

Claims

[Scope of utility model registration request]

(1) Voltage limiting means for limiting a DC voltage that changes between positive and negative to a predetermined range of positive and negative voltages, and a device for outputting a negative voltage that does not saturate when the positive voltage limited by the voltage limiting means is input. a first operational amplifier having a set voltage gain; and a first operational amplifier configured to output zero when a negative voltage limited by the voltage limiting means is input to the first operational amplifier.
The positive and negative voltages limited by the voltage limiting means and the first operational amplifier output voltage are inputted to the first operational amplifier attached circuit, and the first operational amplifier output voltage is doubled to obtain the first operational amplifier voltage gain. and a second operational amplifier that performs an operation of adding the positive and negative voltages limited by the voltage limiting means to the value divided by the value, and outputs the inverted polarity of the result of the operation.

(2) Utility model registration In the absolute value calculation circuit described in claim 1, the voltage limiting means is inserted in series with the DC voltage circuit, and the third calculation is configured such that the output is saturated at a predetermined positive and negative voltage. An absolute value calculation circuit characterized by consisting of an amplifier.

(3) In the absolute value calculation circuit described in claim 1 of the utility model registration claim, the voltage limiting means includes a first diode whose anode is connected to the DC voltage circuit and applies a predetermined positive voltage to the cathode thereof, and the DC voltage. An absolute value calculation circuit characterized by comprising a second diode whose cathode is connected to the circuit and a fixed voltage is applied to the anode of the second diode.