JPS59187224U - Variable limit length circuit - Google Patents

Variable limit length circuit

Info

Publication number
JPS59187224U
JPS59187224U JP8115783U JP8115783U JPS59187224U JP S59187224 U JPS59187224 U JP S59187224U JP 8115783 U JP8115783 U JP 8115783U JP 8115783 U JP8115783 U JP 8115783U JP S59187224 U JPS59187224 U JP S59187224U
Authority
JP
Japan
Prior art keywords
voltage
variable limit
limit length
length circuit
differential amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8115783U
Other languages
Japanese (ja)
Inventor
蝶野 辰夫
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP8115783U priority Critical patent/JPS59187224U/en
Publication of JPS59187224U publication Critical patent/JPS59187224U/en
Pending legal-status Critical Current

Links

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のリミッタ回路の具体的な構成図、−第2
図は本考案の一実施例を示すリミッタ回路の具体的な構
成図である。 7.8・・・増幅器、9. 14. 15・・・抵抗、
10゜11・・・ダイオード、12.13・・・差動増
幅器、16・・・可変抵抗。
Figure 1 is a specific configuration diagram of a conventional limiter circuit.
The figure is a specific configuration diagram of a limiter circuit showing an embodiment of the present invention. 7.8...Amplifier, 9. 14. 15...Resistance,
10゜11...Diode, 12.13...Differential amplifier, 16...Variable resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号に対して逆並列接続のダイオードと、該ダイオ
ードと直列接続の差動増幅器と、該差動増幅器の入力電
圧を設定する可変抵抗とよりなり、入力信号の中心電圧
に対して対称な2つのバイアス電圧を発生するための電
圧発生回路を設け、該バイアス電圧を前記2つのダイオ
ードに各々印加し、該電圧より大きい(または小さい)
電圧の信号が印加された場合は出力電圧値をそれ以上太
きく (または小さく)シないように構成したことを特
徴とする可変リミツテング回路。
It consists of a diode connected antiparallel to the input signal, a differential amplifier connected in series with the diode, and a variable resistor that sets the input voltage of the differential amplifier. A voltage generation circuit for generating two bias voltages is provided, and the bias voltage is applied to each of the two diodes, and the bias voltage is larger (or smaller than the voltage).
A variable limit circuit characterized in that the output voltage value does not increase (or decrease) further when a voltage signal is applied.
JP8115783U 1983-05-31 1983-05-31 Variable limit length circuit Pending JPS59187224U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8115783U JPS59187224U (en) 1983-05-31 1983-05-31 Variable limit length circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8115783U JPS59187224U (en) 1983-05-31 1983-05-31 Variable limit length circuit

Publications (1)

Publication Number Publication Date
JPS59187224U true JPS59187224U (en) 1984-12-12

Family

ID=30211127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8115783U Pending JPS59187224U (en) 1983-05-31 1983-05-31 Variable limit length circuit

Country Status (1)

Country Link
JP (1) JPS59187224U (en)

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