JPS6094541A - Transmitting capacity control circuit device of receiving branch of transmitter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention A transmission device comprises a receive branch and a transmit branch separated from the receive branch, both branches connected by a nor-brid circuit between the transmitter and the receiver. A receiving branch of the transmission device is connected to a 72-wire transmission line via a 72-wire transmission line, an echo suppression circuit is provided between the receiving branch and the transmitting branch, and an amplifier is further provided in the receiving branch. The present invention relates to a circuit device that controls transmission capability.

PRIOR ART Circuit arrangements of the above type are already generally known (for example, from ``IEEE Transactions on Co., Ltd.'').
mmun-ications J Vol, Com, 3
0. No. 9. September 1982, pages 2086-2
094 or German Patent No. 2944486).

Problem to be Solved by the Invention With this known circuit arrangement, a difficulty arises when the known circuit arrangement resumes normal operation after a break in each two-wire transmission line. That is, in the event of such a wire break, each echo suppression circuit is adjusted in such a way that it exactly compensates for the signal components that are sent out from the associated transmitting branch and crosstalk to the associated receiving branch in the event of such a wire break. When operation is restarted after the interruption of the two-wire transmission line, each echo suppression circuit is
Adjustments must first be made in accordance with the changed conditions until the data signal sent by the other subscriber, designated as the partner station, is received without error. In this case, in order to prevent erroneous data signals from reaching the data terminal equipment connected to the circuit arrangement of the type mentioned at the outset, reception of the data signals must be prevented during the compensation process of the latter. For this purpose, for example, a timing element is used.

However, this does not make it possible to set the time intervals in which the reception of data signals is or should actually be blocked, depending on the actual situation in question.

The object of the invention is therefore to ensure that the echo suppression circuit has already been accurately adjusted and the level has exceeded a predetermined threshold value, that is to say that the adjustment process carried out in the associated receiving branch has caused the level fluctuation to fall below a predetermined degree. The object of the present invention is to provide a means by which data signal reception can be started in a relatively simple manner from the beginning.

Means for Solving the Problem This problem, according to the present invention, is to provide a level indication signal indicating whether a predetermined level is occurring or not, and a level indication signal indicating level fluctuation, in a circuit device of the type mentioned at the beginning. The output circuit of the amplifier can transmit a signal only when a level variation instruction signal indicating that a predetermined level is below a predetermined level variation is generated at the same time as a level variation instruction signal indicating that a predetermined level has occurred. It is solved by logically combining each other so that

Example Next, embodiments of the present invention will be described in detail with reference to the drawings.

The circuit device of the present invention shown in FIG.
It is equipped with a four-way transmission line having J and '. As shown in FIG. 1, a data terminal DEE is connected to the transmission line SL and the reception line EL', and this data terminal is, for example, a device capable of transmitting and receiving data signals.

The four-wire transmission line explained above is a hybrid circuit He
is connected to a two-wire transmission line ZD, which can be used for full-duplex communication transmission of data.

Furthermore, the input side of the echo suppression circuit Cam is connected to the transmission line SL. The output side of this circuit Com is an addendum, a device A
dd1, and the other input side of the adder 4 is connected to the output terminal of the hybrid circuit Hc on the 4-wire line side. This echo suppression circuit Com
The control input side of is connected to the output side of a control amplifier Op, which is, for example, an operational amplifier, whose inverting input side is connected to the ground, and the non-inverting input side is connected to the output side of the adder Add1 mentioned above, and thus to the output side of the adder Add1. It is connected to the receiving line EL.

According to FIG. 1, an amplifier Am with adjustable amplification, in particular a digitally adjustable amplifier, is connected to the receiving branch of the Am transmission line. At that time, the amplification degree of amplifier Am is
It can be adjusted by means of two signals which are applied to the corresponding control inputs of this amplifier.

The output of the amplifier Am is connected to one input of the AND data) G1, and the output of the AND data G1 is connected to the corresponding input of the data terminal DEE via the already mentioned receiving line EL'. The other input of the AND data (11) is connected to the output of a logical combination element G2, which is, for example, an AND gate or a blocking element.

One signal input side of the logical coupling element G2 is connected to the output side of the level monitoring detector Det1, and the other input side or negative input side is connected to the output side of the level fluctuation detector Det2.

The rain detectors Det1 and Det2 are commonly connected at their input sides to the amplifier A+n, and are connected in such a way that they can detect the respective level increase or level fluctuation of the level of the amplifier Am.

The operation of the circuit device shown in FIG. 1 whose structure has been explained above will now be briefly explained.

A level monitoring device is constituted by a device including rain detectors Det 1 , Det 2 and double wheel coupling elements G1 and G2. The detector Det1 of this device is an amplifier A
It is detected whether a predetermined level occurs in the received signal sent by m.

In contrast, the detector Det2 detects level fluctuations within a predetermined time interval. The signals indicating these detected values are combined by the two ring coupling elements G1 and G2 as follows, that is, the output circuit of the amplifier Am is connected only when AND) f-1-01 is conductive, that is, the output circuit of the detector Det1 is A level indication signal indicating the occurrence of a predetermined level is sent from the output side, and at the same time, a level fluctuation instruction signal is sent from the detector Det2 indicating that there was only a variation less than the predetermined level variation within a predetermined time interval. They are coupled together to enable signal transmission.

Next, an embodiment of the level monitoring device shown in FIG. 2 will be described in detail.

As in Fig. 1, Fig. 2 also shows an amplifier Am, whose input side is connected to the receiving line EL, and whose output side is connected to the
'F'-) is connected to one input side of Gl. AN
The output side of D)f'-)Gl is connected to the receiving line EL'. The other input side of Gl in FIG. 2 is connected to the output side of logic coupling element G2, and the connection configuration of the input side of this logic coupling element G2 with other circuit parts in FIG. will be explained in detail later.

In FIG. 2, the individual register stages B 1 of register Reg1
+ Amplifier A on the output side of B 2 HB 3 or B4
m series of control inputs are connected, the register being a register with parallel inputs and parallel outputs.

The register Reg 1 is supplied with clock pulses at its control input or clock input C1 and has a parallel input connected to each output of the individual adder stages of a full adder Add1. One input side of the adder stage, designated as a input Gltl, is respectively connected to the corresponding parallel output side of register stages B1 to B4 of register i (eg l. This allows each register stage of register Reg 1 to B
The output 14Uj of 1 to B4 and the input side are adders Add1
are connected via one adder stage each.

The other input of the full adder Add l, indicated as the b input, is connected in FIG. 2 to the D (down) output of a level monitoring or thresholding device Pw. The level monitoring-threshold device Pw has an input (till) connected to the signal output or control output of the amplifier Am,
Monitor the level with respect to a predetermined level or threshold.

The signal on the D (down) output side acts to reduce the value stored in the register Reg 1, which in turn acts to cause a corresponding amplification change in the amplifier Am.

Carry (or Carry-In) of adder Add1
The input side Ac is connected to the U (up) output side of the threshold device Pw. The signal on this U output side is the register Reg
It acts to increase the value of the memory contents of No. 1, and changes the degree of amplification accordingly. .

According to FIG. 2, the input of a level detector Det 1 is connected to the output of the register stage of the register Reg1. This level detection 5Det1 is shown in FIG. 2 as one level detector equipped with one logical coupling element.

However, the level detector Det'l may also have a plurality of logic coupling elements, and these logic coupling elements have an output when a combination of bits corresponding to a predetermined level is applied to the input of the detector. For example, a binary signal "1pa" is sent out.The output side of the level detector Det1 is further connected to the signal input side of the above-mentioned logical coupling element G2.

The input side of EXOR gate G3 is connected to the input side and output side of register stage B1 of register Reg1. The output side of this EXOR gate is connected to the control input side of the changeover switch S and the input side of AND r"-) G5. The other input side of this AND gate G5 is connected to another E
xoRr-) a Connected to the output side of 4. Another EXOR key) One input terminal of G4 or register Re
Input of register stage B2 of g1? +1! The other input side is connected to the non-inverting output side of the D-Fri Ruff 0 Flotso. The data input side of this 1] flip-flop FF is connected to the switching contact of a changeover switch S, and this changeover switch is in one switching position (゛0'°
It is connected to the output side of the D flip-flop at the position VC, and connected to the output of the register B2 of the register I (6gi) at the other switching position (1 pin position R).

The clock input of the D flip-flop is supplied with the same clock pulses or control pulses that are supplied to the clock input c1. This D Frizzo Frozzo li'
F is the logical coupling element a3. G4. Together with G5, it constitutes a level fluctuation detector 1) et 2. This detector D
ANI of et2) The output side of gate G5 is an inverting delay element 0.
6 to one input terminal of the above-mentioned logical coupling element G2.

The operation of the level monitoring device shown in FIG. 2, the structure of which has been explained above, will be briefly described below.

First, the level detection e Det is input to the register Re, g1.
Assume that a binary number is stored such that i sends a binary signal "o" to the output side. As a result, the logical coupling element G
2 sends out a binary signal "0", and since the AND gate G1 is blocked, the signal sent out from the amplifier Am cannot reach the receiving line EL'.

If a correspondingly high level is applied to the amplifier Am via the reception line EL, the value +1 is applied from the U (up) output of the threshold switch Pw to the adder Add1. Each such value +1 has the effect that the binary number applied to the input of the corresponding adder Add1 is increased by the value 1 and sent to the output. The binary number delivered from the output of the adder Aaa 1 is applied to the parallel input of the register Reg 1 and, when the next clock pulse is applied to the clock input C1, is transferred to the register stages B 1 to B4 of the register. Subsequently, the parallel output sides of register stages B1 to B4 of register Reg 1 are connected to the input side of adder Add1 and level detector Det.
, 1 and outputs the corresponding binary number on the input side. When the predetermined level is not reached again, this level detector Det 1
continues to send a binary signal "0" to the output side. This is the second
This corresponds to the situation described above with respect to the theory of operation of the illustrated circuit. On the other hand, the level detector Det1 detects a predetermined level -
When the signal has passed L times (Kanayama), a binary signal "1" is sent from the detector output side, and as a result, it becomes possible to control the logic coupling element G2 to a conductive state in principle.Logic coupling element G
2 in the conductive state iI4+L, and thus in order to enable further transmission of the data signal via the AND gate G1, a binary signal "AND)" is output from the output of f-1-05.
The i'IiI proposition for transmitting ``o'' will be explained in detail below.

If a combination bit of 0000 occurs in register Reg 1 starting from register stage B4, this indicates that the adjustment of amplifier A11l is still insufficient. When this combination bit is increased by 1, a new combination bit of 0001 is applied to the input of this register stage. In this case, EXOR gate G3 is 2
Sends a forward signal "i", and this signal is sent to the selector switch S.
The control signal flt is supplied to the input terminal ``flt'' and one input side of the AND gate G5. When this signal occurs, the D flip-flop FF receives the signal (binary signal This means that the binary signal "0" is further sent out from the output side of the EXOR gate G4. Therefore, AND gate G5 also sends out a binary signal "o". When the adder Add1 further adds 1/1, a combination bit of 0010 is supplied to the parallel input terminals of the register stages B4 to B1 of the register Regl. As a result, a binary signal "1" is again sent out from the output side of EXOR data G3, and a binary signal "0" is sent out from the output side of the D flip-flop FF. The difference from the case explained earlier is that EXOR game) 04
On the other input side of , there is now a binary signal "1" Kerr force V, so that in this case a binary signal "1" is applied to both input sides of AND date ()5. Therefore AND r −
) G5 delivers at its output a binary signal "1"', which interrupts the logic coupling element G2 via the inverting delay element G6.

Combination picks from 0000 to the above combination picks
The transition of the combination bit 0010-\ through -0001 strictly only concerns two level increases (or decreases -01/10) in register stages B i and B2 of register Reg 1, and this represents the level fluctuation when the logical coupling element G2 is cut off. The switching off of the logic coupling element G2 is carried out as follows: 1] Flip 070 tube I? The output signal of F is delayed by one change in register stage B1 (this change is an EXOR game) with respect to the state of register stage B1, and the change in the output level of register stage B2 is This is done by delaying the level Ki on the input side of register stage B2. In other words, in terms of time, two state changes for register stage B1 occur between the input level or input signal of register stage B2 and the output L/bevel of D flip-flop FF. In other words, a mismatch between the output signal of the D flip-flop' FF and the input signal of the register stage B2 is detected only when the level increases (or decreases) continuously, and the Advance signal “1”
”. This results in AJqDw” -G
5 sends out a binary signal "1", which is passed through the inverting delay element G6 to the logical coupling element G2 (and is AND r
” - Cut off G1.

In case of insufficient level, the logical coupling element G2 is cut off by the output of the level detector Det 1 and the register R
If the combination bit of eg 1 changes significantly (this is indicated by the combination bit rising or falling for the second time), the output of the level detector Det2 shuts off the logical coupling element G2. When the combination bits in register stages B1 to B4 of register Regl are held, i.e. when the addition process does not develop any further, or simply 1 addition-subtraction 1 addition 1 subtraction... is only repeated (this is D flip-flop 1
1') and the level variation detector Det
A binary signal "0" is sent from 2. Then, the output of the logical coupling element G2 (the binary signal "1" is sent from Ill to the AND gate G1, and then the AND gate) G1 transmits the signal sent from the output side of the amplifier Am to the receiving line EL'. do.

From the above description of the level monitoring device shown in FIG. 2, the following is clear. In other words, the absolute value of the level height at each time is such that the data signal from the output side of the amplifier is connected to the receiving line EL'.
Not only can it be used as a criterion for determining whether or not the signal can be transmitted, but also the level variation that has occurred, that is, the amplifier adjustment signal that caused this level variation, can also be used as the criterion. Only when this level fluctuation falls below a predetermined value, i.e. becomes stable, does this predetermined value determine that, if a sufficient signal level is applied, the signal emitted by the amplifier Am will be transmitted to the receiving line E.
It is used as a reference to be transmitted to L'.

With respect to the above-mentioned inverting delay element G6, it is advantageous to select its delay time to include the (adjusted) rise time of the amplifier, thereby forming a safety time interval.

Effect of the invention: With the configuration of the present invention, after the compensation adjustment acting on the reception branch of the transmission device is virtually completed, that is, on the one hand, a sufficient reception level is added, and on the other hand, a large level fluctuation occurs in the compensation signal and thus in the reception signal. Once this is no longer the case, this receiving branch can begin the data signal receiving operation, which can be implemented at low cost in terms of circuit technology.

With the configuration described in claim 2, it is possible to detect each level and level fluctuation relatively easily.

The arrangement according to claim 6 provides a highly advantageous and relatively simple construction of the level monitoring device, which can be relatively easily produced in integrated circuit technology.

With the configuration described in claim 4, the above-mentioned level monitoring device can be used for both level detection and level fluctuation detection.
・Be able to do things.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a circuit arrangement of the present invention, and FIG. 2 is a detailed block circuit diagram of an embodiment of a level monitoring device used in the circuit arrangement of FIG. Am...Amplifier, Detl...Level detector, Det
l...Level fluctuation detector, Regl...Register,
S...Switch, F'F...D flip flow rough'
, G6...inverting delay element

Claims (1)

[Claims] 1. The transmission device includes a receiving branch and a transmitting branch separated from the receiving branch, and both of these branches connect an hybrid circuit (Hc) between the transmitter and the receiver. through 2
It is connected to a wire transmission line (ZD), and an echo suppression circuit (Com, Op, A
Indicates whether a predetermined 17 bells are occurring in a circuit device that controls the transmission capability of the receiving branch of the transmission device, in which the receiving branch is provided with a dd 1) and an amplifier (Am) is provided in the receiving branch. The level instruction signal 1 and the level variation instruction signal indicating the level variation are combined to generate a level variation instruction signal indicating that the level variation is below the predetermined level variation at the same time as the level instruction signal indicating the occurrence of the predetermined level. characterized in that the output circuits of the amplifiers (Am) are logically coupled to each other so that signal transmission is possible only when
A transmission capacity control circuit device for a receiving branch of a transmission device. 2. An amplifier (Am) whose amplification degree can be adjusted digitally with multiple bits is provided, and a level monitoring device (De t
1 + 'De't 2 + G 2 T G 1
), and the level monitoring device monitors the difference from a predetermined bit pattern of the digital signal occurring at continuous amplification adjustment points. Transmission capacity control circuit device for receiving branch. 6. Clock controllable register (Reg 1) with parallel input and parallel output in the level monitoring device
and an adder (Addl), through which the parallel output side of the register (Reg 1 ) is connected to the corresponding parallel input side of this register, and
The input side of the first Eχ0R)f-to (G3) is connected to one parallel input side and the corresponding one parallel output side of 1), and another parallel input side of this register (Reg 1) is connected. The input side of the second EXOR game (G4) is connected to the side, and the register (Re
The signal input side (D) of a clock-controlled bistable multivibrator (F1j゛) is connected to the parallel output side of the first 1.g1). The output side of the tχOR gate (G3) is connected through a switch (S) that can be operated, and the bistable multivibrator (FF) is connected to the switch (S).
is connected to the (non-inverting) output side of this bistable multivibrator through the
Connect the other input 1tllll of the gate, and connect both E
A transmission capacity control circuit device for a receiving branch of a transmission device according to claim 2, wherein the output side of the XOR gate (G3, G4) is connected to the input end of the AND dart (G5). 4.ANI) Combine the output signal of Key-1-(G5) with a signal corresponding to a predetermined amplification degree or a corresponding bit pattern in the register (Reg 1) via an inverting delay hexagon (G6). 4. A control circuit device for controlling the transmission capacity of a reception branch of a transmission device according to claim 3, wherein the control circuit device forms a control signal for controlling the transmission capacity of the reception branch.