JPS609234U - electronic components - Google Patents
electronic componentsInfo
- Publication number
- JPS609234U JPS609234U JP10258883U JP10258883U JPS609234U JP S609234 U JPS609234 U JP S609234U JP 10258883 U JP10258883 U JP 10258883U JP 10258883 U JP10258883 U JP 10258883U JP S609234 U JPS609234 U JP S609234U
- Authority
- JP
- Japan
- Prior art keywords
- leads
- electronic components
- coating layer
- lengths
- electronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は電子部品の一例を示す一部透視平面図第2図は
半田ブリッジを生じた電子部品の平面図第3図はリード
の断面図、第4区は断面形状による半田の付着状況を説
明するリードの断面図、第5図は本考案の一実施例を示
す平面図、第6図及び第7図は本考案の他の実施例を示
す平面図であ。 る。
2・・・・・・部品本体、6・・・・・・半田被覆層、
7・・・・・・す、 −ド。Fig. 1 is a partially perspective plan view showing an example of an electronic component. Fig. 2 is a plan view of an electronic component with solder bridges. Fig. 3 is a cross-sectional view of a lead. Section 4 shows the solder adhesion situation depending on the cross-sectional shape. FIG. 5 is a plan view showing one embodiment of the present invention, and FIGS. 6 and 7 are plan views showing other embodiments of the present invention. Ru. 2... Part body, 6... Solder coating layer,
7...su, -do.
Claims (1)
導出しかつ、リードにディップ法による半田被覆層を形
成したものにおいて、隣接するリードの長さを異ならせ
たことを特徴とする電子部品。An electronic device characterized in that a plurality of leads are led out in the same direction from the main body of the component using a parallel front handle, and a solder coating layer is formed on the leads by a dipping method, and the lengths of adjacent leads are made different. parts.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10258883U JPS609234U (en) | 1983-06-29 | 1983-06-29 | electronic components |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10258883U JPS609234U (en) | 1983-06-29 | 1983-06-29 | electronic components |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS609234U true JPS609234U (en) | 1985-01-22 |
Family
ID=30241736
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10258883U Pending JPS609234U (en) | 1983-06-29 | 1983-06-29 | electronic components |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS609234U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244658A (en) * | 1987-03-30 | 1988-10-12 | Mitsubishi Electric Corp | Semiconductor device |
-
1983
- 1983-06-29 JP JP10258883U patent/JPS609234U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244658A (en) * | 1987-03-30 | 1988-10-12 | Mitsubishi Electric Corp | Semiconductor device |
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