JPS6089255A - Trouble informing system in decentralized processing type bus system - Google Patents
Trouble informing system in decentralized processing type bus systemInfo
- Publication number
- JPS6089255A JPS6089255A JP58195735A JP19573583A JPS6089255A JP S6089255 A JPS6089255 A JP S6089255A JP 58195735 A JP58195735 A JP 58195735A JP 19573583 A JP19573583 A JP 19573583A JP S6089255 A JPS6089255 A JP S6089255A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- processors
- master
- bus
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の分り’Ｆ ）
本発明は、分散処理系バスシステムに於る異常障害通知
方式に関する。DETAILED DESCRIPTION OF THE INVENTION (Aspects of the Invention) The present invention relates to an abnormal failure notification system in a distributed processing bus system.
（従来技術）
従来の分散処理系バスの各プロセサの異常障害通知処理
では、異常障害を発生したプロセサがマスタープロセサ
のプロセサアドレスによって、異常障害発生信号を通知
するという方式であった。(Prior Art) In the conventional abnormal failure notification process for each processor of a distributed processing bus, the processor in which the abnormal failure has occurred notifies an abnormal failure occurrence signal using the processor address of the master processor.
従って同一のバス内にアクト系マスクプロセサ及びスタ
ンドバイ系マスクプロセサが接続され、該マスタープロ
セサを任意に切り換える制御機能を具備する分散処理系
バスシステムの場合、各ノードではアクト系のマスター
プロセサのアドレスが認識できず、障害異常信号をアク
ト系マスタープロセサに通知する事ができないという欠
点があった。Therefore, in the case of a distributed processing bus system in which an active mask processor and a standby mask processor are connected to the same bus, and which has a control function to arbitrarily switch the master processor, each node has the address of the active master processor. It had the disadvantage that it could not recognize the error signal and could not notify the act system master processor of the failure abnormal signal.
（発明の目的）
本発明は、障害異常発生のプロセサがバス上の全てのブ
ロセチヘ、回報機能を用いて障害異常信号を通知し、ア
ドレス不定のアクト系−マスタープロセサに、障害異常
を発生したプロセサをに忍識させる事により、上記欠点
を解決した分散処理系ノ（スジステム異常障害通知方式
を提供することにある。(Purpose of the Invention) The present invention provides for a processor in which a fault has occurred to notify a fault abnormal signal to all blocks on the bus using a communication function, and to notify the processor in which a fault has occurred to an act system with an undefined address - a master processor. The object of the present invention is to provide an abnormal failure notification system for distributed processing systems that solves the above-mentioned drawbacks by making people aware of the above problems.
（発明の構成）
本発明は、同一のバスに、複数のブ１１セサと、アクト
系のマスタープロセサと、スタツフ（イ系のマスタープ
ロセサとが接続され、前記両マスタープロセサを任意に
切り換え可能な制御機能を具備する分散処理系バスシス
テムに於て、
各プロセサが信号をバス内の他の全てのプロセサ及びマ
スタープロセサに同時に通知可能な回報機能を具備し、
前記プロセサの少なくとも７つに障害が発生した時に、
該プロセサは該同＠４機能により、障害異常信号を全プ
ロセサ及びマスタープロセサに通知する事により、プロ
セサアドレスが不定のアクト系マスタープロセサに該プ
ロセサの障害異常を認識させるようにした事を特徴とす
る。(Structure of the Invention) The present invention is characterized in that a plurality of bus processors, an act master processor, and a staff master processor are connected to the same bus, and the two master processors can be switched arbitrarily. In a distributed processing bus system equipped with a control function, each processor is equipped with a relay function that allows it to simultaneously notify signals to all other processors in the bus and the master processor,
when at least seven of the processors fail;
The processor is characterized in that the @4 function notifies all processors and the master processor of a fault abnormality signal, thereby causing an active master processor with an undefined processor address to recognize the fault abnormality of the processor. do.
（発明の実施例）
以下図面を参照して本発明の一実施例を説明する。第１
図は、本発明の一実施例のブロック図であって、バス（
ＢＵ８ α）には、それぞれバス制御装置（Ｂｅ／〜Ｂ
Ｃ，！ｔ）を介して、プロセサ（ＰＩ。(Embodiment of the Invention) An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of an embodiment of the present invention, and shows a bus (
BU8 α) has a bus control device (Be/~B
C,! t) through the processor (PI.
Ｐ２．Ｐ’３）、マスクプロセサ（ＭＰ／ 、ＭＰ、２
）が接続されている。マスタブープロセサ（ＭＰ／、Ｍ
Ｐ２）には、プロセサ（ｐ／、ｐ２．ｐＪ）に影響を与
えることなく、マスタープロセサ（ＭＰ／とＭｐＪ）を
切り換えることができるアクト／スタンドバイ制御装置
（ＡＳＣ）が接続されている。プロセサ（ｐ／、ｐＪ、
ｐＪ）は自己の機能の障害異常を認識することが可能で
あり、バス制御装置（Ｂｅ／〜ＢＣ，ｌｔ）は、バス（
ＢＵＳα）に接続された他のプロセサ（Ｐ／〜Ｐ、？）
、マスタープロセサ（ＭＰ／：ＭＰ２＞に障害異常信号
を同時に通知可能な回報機能を備えており、更にバス（
ＢＵＳα）からの信号に影響を与えることなく、それぞ
れ自己のプロセサ（Ｐ／〜Ｐ３）、マスタープロセサ（
ＭＰ／ＭＰ２）Ｋ障害異常信号を通知することができる
。P2. P'3), mask processor (MP/ , MP, 2
) are connected. Master Boo Processor (MP/, M
P2) is connected to an act/standby control device (ASC) that can switch the master processors (MP/ and MpJ) without affecting the processors (p/, p2.pJ). Processor (p/, pJ,
The bus controller (Be/~BC, lt) can recognize the failure abnormality of its own functions, and the bus controller (Be/~BC, lt)
Other processors (P/~P, ?) connected to BUSα)
It is equipped with a relay function that can simultaneously notify the master processor (MP/:MP2>) of failure abnormal signals, and also has a relay function that can simultaneously notify the master processor (MP/:MP2>
The respective processors (P/~P3) and master processor (
MP/MP2)K failure abnormal signal can be notified.
なお、上記構成において、プロセサ（Ｐ／〜Ｐ３）は、
マスタープロセサ（ＭＰ／、ＭＰ、２）のいずれに接続
されているか、すなわちマスタープロセサ（ＭＰ／１Ｍ
Ｐ２）のいずれがアクト系マスタープロセサなのか認識
することができない。In addition, in the above configuration, the processor (P/~P3) is
Which of the master processors (MP/, MP, 2) is connected to, that is, the master processor (MP/1M
It is not possible to recognize which one of P2) is the act master processor.
今、たとえばプロセサ（ＰＩ）が、アクト／スタンドバ
イ制御装置（ＡＳＣ）Ｋよりマスタープロセサ（ＭＰ／
）に切り換えられているとすれば、マスタープロセサ（
ＭＰ／）がプロセサ（ＰＩ）のアクト系マスタープロセ
サとなり、マスタープロセサ（ＭＰ２）がスタンドバイ
系マスタープロセサとなる。ここでプロセサ（ＰＩ）に
障害異常が発生した場合を仮定すると、プロセサ（ＰＩ
）は該障害異常を認識し、障害異常信号に自己のプロセ
サアドレスを附加した信号囚をバス制御装置（ＢＣ／）
に印加し、バス制御装置（ＢＣ／）は信号Ａをそれぞれ
バス制御装置（ＢＣ，，２〜ＢＣ，ｔ）を介してプロセ
サ（Ｐ２．Ｐ３）、マスタープロセサ（ＭＰ／ＭＰ、２
）に通知する。この場合、プロセサ（Ｐ２．Ｐ３）及び
マスタープロセサ（λＩＰ２）は、プロセサ（ＰＩ）の
アクト系マスタープロセサでないため何らの処理を行な
わず、他方、マスタープロセサ（ＭＰ／）はプロセサ（
ＰＩ）の障害異常を認識する。Now, for example, if the processor (PI) is more active than the master processor (MP/
), the master processor (
MP/) becomes the active master processor of the processor (PI), and the master processor (MP2) becomes the standby master processor. Here, assuming that a failure abnormality occurs in the processor (PI),
) recognizes the fault abnormality and sends the signal that has added its own processor address to the fault abnormal signal to the bus control device (BC/).
The bus controller (BC/) sends the signal A to the processors (P2, P3) and master processors (MP/MP, 2) via the bus controllers (BC,, 2 to BC, t), respectively.
). In this case, the processors (P2, P3) and the master processor (λIP2) do not perform any processing because they are not act-type master processors of the processor (PI), and on the other hand, the master processor (MP/)
Recognize the failure abnormality of PI).
（発明の効果） 本発明は以上説明した様に、分散処理システム 。(Effect of the invention) As explained above, the present invention is a distributed processing system.
においてバスに接続されているプロセサの障害異常通知
方式において、障害異常が発生したプロセサが同一バス
内に障害異常通知信号を回報で送ることにより、従来不
可能であったアドレス不定のマスタープロセサの障害プ
ロセサのアドレス認識をｉｑ能にする効果がある。In the failure abnormality notification system for processors connected to a bus, the processor in which the failure has occurred sends a failure abnormality notification signal within the same bus, thereby detecting a failure of a master processor with an unspecified address, which was previously impossible. This has the effect of making the address recognition of the processor iq-enabled.
第１図は本発明の一実施例のブロック図である。
ＰＩ、Ｐ２．Ｐ３・・・・・・プロセサ。
ＢＣ／〜Ｆ３ＣＪ・・・・・・バス制御装置。
ＭＰ／、ＭＰ’２・・・・・・マスタープロセサ。
ＡＳＣ・・・・・・・・・・・・アクト／スタンバイ切
り換え制御装置。
ＢＵ８α・・・・・・・・・・・・分散処理系バス。
信号Ａ・・・・・・・・・・・・プロセサ°Ｐ／の異常
障害信号。FIG. 1 is a block diagram of one embodiment of the present invention. PI, P2. P3...Processor. BC/~F3CJ...Bus control device. MP/, MP'2... Master processor. ASC・・・・・・・・・Act/standby switching control device. BU8α・・・・・・・・・Distributed processing bus. Signal A: Abnormal failure signal of processor °P/.
Claims (1)
タープロセサと、スタンバイ系のマスタープロセサとが
接続され、前記両マスタープロセサを任意に切り換え可
能な制御機能を具イｄ＃する分散処理系バスシステムに
於て、 各プロセサが信号をバス内の他の全てのプロセサ及びマ
スタープロセサに同時に通知可能な回報機能を具備し、
前記プロセサの少なくとも／っに障害が発生した時に、
該プロセサは該回報機能により、障害異常信号を全プロ
セサ及びマスタープロセサに通知する事により、プロセ
サアドレスが不定のアクト系マスタープロセサに該プロ
セサの障害異常を認識させるようにした事を特徴とする
分散処理系バスシステムにおける異常障害通知方式。[Scope of Claims] A plurality of processors, an active 7-star processor, and a standby master processor are connected to the same bus, and a control function is provided to enable arbitrary switching between the two master processors. In a distributed processing bus system, each processor has a relay function that allows it to simultaneously notify all other processors in the bus and the master processor,
When a failure occurs in at least one of the processors,
The processor is characterized in that the relay function notifies all processors and the master processor of a fault abnormality signal, thereby causing an act system master processor whose processor address is undefined to recognize the fault abnormality of the processor. Abnormal failure notification method in processing bus system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195735A JPS6089255A (en) | 1983-10-19 | 1983-10-19 | Trouble informing system in decentralized processing type bus system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195735A JPS6089255A (en) | 1983-10-19 | 1983-10-19 | Trouble informing system in decentralized processing type bus system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6089255A true JPS6089255A (en) | 1985-05-20 |
Family
ID=16346088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58195735A Pending JPS6089255A (en) | 1983-10-19 | 1983-10-19 | Trouble informing system in decentralized processing type bus system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089255A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4874505B2 (en) * | 2000-10-27 | 2012-02-15 | 善信 新田 | heating furnace |
-
1983
- 1983-10-19 JP JP58195735A patent/JPS6089255A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4874505B2 (en) * | 2000-10-27 | 2012-02-15 | 善信 新田 | heating furnace |
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