JPS6089122A - Phase comparator circuit - Google Patents
Phase comparator circuitInfo
- Publication number
- JPS6089122A JPS6089122A JP58195994A JP19599483A JPS6089122A JP S6089122 A JPS6089122 A JP S6089122A JP 58195994 A JP58195994 A JP 58195994A JP 19599483 A JP19599483 A JP 19599483A JP S6089122 A JPS6089122 A JP S6089122A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- circuit
- gate
- reference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Control Of Electric Motors In General (AREA)
- Control Of Direct Current Motors (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はモータの制御回路等に用いられる位相比較回路
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase comparator circuit used in a motor control circuit or the like.
従来例の構成とその問題点
第１図は従来から用いられている基本的な位相比較回路
の一例である。端子１には第１の基準パルスが加えられ
る。端子２からは、モニタの回転数検出器の出力、すな
わちＦＧパルスが入力される。Ｓ／Ｒフリップフロップ
３は第１の基準パルスによってセットされ、ＦＧパルス
によってリセットされる。端子４からは、２つの信号の
位相差に相当するパルス巾のパルスが出力される。第２
図は第１図の回路のタイムチャートである。Structure of the conventional example and its problems FIG. 1 shows an example of a basic phase comparator circuit that has been used in the past. A first reference pulse is applied to terminal 1. From terminal 2, the output of the rotation speed detector of the monitor, that is, the FG pulse is input. The S/R flip-flop 3 is set by the first reference pulse and reset by the FG pulse. A pulse with a pulse width corresponding to the phase difference between the two signals is output from the terminal 4. Second
The figure is a time chart of the circuit of FIG.
一般に、モータ等の制御回路にこの様な位相比較回路を
用いる場合、モータをなめらかに回転させる為に、Ｓ／
Ｒフリップフロッグ３の出力する位相誤差パルスを口〜
パスフィルタによって平滑する必要がある。ところがロ
ーパスフィルタは位相遅れを生ずる為、制御系の過渡応
答特性が悪化するという問題がある。Generally, when using such a phase comparator circuit in a control circuit for a motor, etc., in order to rotate the motor smoothly, the S/
Input the phase error pulse output from R flip frog 3.
It is necessary to smooth it with a pass filter. However, since the low-pass filter causes a phase lag, there is a problem in that the transient response characteristics of the control system deteriorate.
発明の目的
本発明は、モータの制御回路に用いた場合にも、上記過
渡応答特性とモータのなめらかな回転を両立させること
のできる位相比較回路を提供するものである。OBJECTS OF THE INVENTION The present invention provides a phase comparator circuit that can achieve both the above transient response characteristics and smooth motor rotation even when used in a motor control circuit.
発明の構成
本発明は、第１の信号を、第１の基準信号の周期の１／
ｎ、２／ｎ・・・：・・（ｎ−１）／ｎだけ遅らせた第
へ１戸第２（２戸・・・・・第２（ｎ−１）の信号を作
り、前記第１の基準信号の１／ｎ の周期を持つ第２の
基準信号と、前記第１．第２（１）’第２（匂・・・・
・・第２（ｎ−１）の信号を合成して得られる第３の信
号の位相比較出力をもって、第１の基準信号と、第２の
信号と位相差となすようにしたものである。Structure of the Invention The present invention provides a first signal with a period of 1/1 of the period of the first reference signal.
n, 2/n...:...Create a signal for the 1st door 2nd (2nd door...2nd (n-1)) delayed by (n-1)/n, and a second reference signal having a period of 1/n of the reference signal;
...The phase comparison output of the third signal obtained by combining the second (n-1) signals is made to have a phase difference between the first reference signal and the second signal.
実施例の説明 第３図は本発明のｎ ＝ ２の場合の一実施例を示す。Description of examples FIG. 3 shows an embodiment of the present invention when n=2.
１〜４については第１図と同一である為、説明を省略す
る。但し、第３図の端子１から入力される基準パルス（
第２の基準パルスとする）は、同期状態におけるＦＧパ
ルスの％の周期を持っている。端子２から加えられるＦ
Ｇパルスは、遅延回路５によって正確に第２の基準パル
スの１周期ＴＯ分遅れ、信号Ａとなる。ＦＧパルスと信
号ＡはＯＲゲート６０２つの入力となυ、その出力信号
Ｂはフリップフロップ３のリセット入力となる。1 to 4 are the same as those in FIG. 1, so their explanation will be omitted. However, the reference pulse input from terminal 1 in Figure 3 (
The second reference pulse) has a period of % of the FG pulse in the synchronous state. F applied from terminal 2
The G pulse is delayed by exactly one cycle TO of the second reference pulse by the delay circuit 5, and becomes the signal A. The FG pulse and the signal A are two inputs to the OR gate 60, and its output signal B is the reset input to the flip-flop 3.
そして第２の基準パルスと信号Ｂの位相差に相当するパ
ルス幅のパルスが端子４がら出力される。Then, a pulse having a pulse width corresponding to the phase difference between the second reference pulse and signal B is outputted from the terminal 4.
図の位相誤差パルスに比べ、第４図の位相誤差パルスの
周波数は２倍になっている。もちろん、第２の基準パル
スとして、同期状態におけるＦＧパルスの１／ｎ の周
期を持つものを使用すれば、位相誤差パルスの周波数を
ｎ倍にすることができる。The frequency of the phase error pulse in FIG. 4 is twice that of the phase error pulse in the figure. Of course, if a second reference pulse having a period of 1/n of the FG pulse in the synchronized state is used, the frequency of the phase error pulse can be increased by n times.
なお、この実施例においては第３図の第２の基準パルス
が第２の基準信号に、ＦＧパルスが第１又、第１の基準
信号は、水晶等の発振信号を分周して、第２の基準信号
を作る過程で得られる（分局が一回少ない）為に、本実
施例では図示を省略している。In addition, in this embodiment, the second reference pulse in FIG. Since this signal is obtained in the process of creating the second reference signal (with fewer branching operations), it is not shown in the figure in this embodiment.
発明の効果
本発明を用いる事にょシ、同じＦＧ倍信号使用しても、
位相誤差パルスの周波数をｎ倍に上げる事が出来る。し
たがって制御ループに構成されるローパスフィルターの
カットオフ周波数を上げる事が出来、過渡特性の劣化を
防ぐ事が出来る。過渡特性と静粛な回転の要求されるレ
コードプレーヤ等の音響装置において特に効果が太きい
。Effects of the invention By using the present invention, even if the same FG multiplication signal is used,
The frequency of the phase error pulse can be increased by n times. Therefore, it is possible to increase the cutoff frequency of the low-pass filter configured in the control loop, and it is possible to prevent deterioration of transient characteristics. This is particularly effective in audio equipment such as record players that require transient characteristics and quiet rotation.
第１図は従来の位相比較回路のブロック図、第２図は第
１図の位相比較回路のタイムチャート、第３図は本発明
の一実施例のブロック図、第４図は第３図の実施例のタ
イムチャートである。
１．２．４・・・・・・端子、３・・シ・・・セットリ
セットクリップフロップ、５・・・・・・遅延回路、６
・・・・・・ＯＲゲート。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
Ｆ４ハ０ノＣス
第２図
第３図
第４図FIG. 1 is a block diagram of a conventional phase comparison circuit, FIG. 2 is a time chart of the phase comparison circuit of FIG. 1, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of the phase comparison circuit of FIG. It is a time chart of an example. 1.2.4...Terminal, 3...Set reset clip-flop, 5...Delay circuit, 6
...OR gate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure F4 HA0NOC Figure 2 Figure 3 Figure 4
Claims (1)
）’第２（２）。 ・・・・・・第２（ｎ−１）の信号を作る遅延回路と、
前記第１の基準信号の１／ｎの周期を持つ第２の基準信
号と前記第１．第２（１）’第２い〕・・・・・・第２
（ｎ−１）の信号を合成して得られる第３の信号との位
相を比較する位相比較器とを備えた事を特徴とする位相
比較回路。[Claims] The first signal has a period of 1/n of the period of the first reference signal. 2/n...(" Delay by 1)/n and start the second (1
)'Second (2). ... a delay circuit that generates a second (n-1) signal,
a second reference signal having a period 1/n of the first reference signal; and a second reference signal having a period of 1/n of the first reference signal; 2nd (1)'2nd]...2nd
A phase comparison circuit comprising: a phase comparator that compares the phase with a third signal obtained by combining (n-1) signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195994A JPS6089122A (en) | 1983-10-21 | 1983-10-21 | Phase comparator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195994A JPS6089122A (en) | 1983-10-21 | 1983-10-21 | Phase comparator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6089122A true JPS6089122A (en) | 1985-05-20 |
| JPH0463633B2 JPH0463633B2 (en) | 1992-10-12 |
Family
ID=16350449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58195994A Granted JPS6089122A (en) | 1983-10-21 | 1983-10-21 | Phase comparator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089122A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5551100U (en) * | 1978-10-02 | 1980-04-03 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5376215A (en) * | 1976-12-18 | 1978-07-06 | Mazda Motor Corp | Suction appatatus of sngine |
-
1983
- 1983-10-21 JP JP58195994A patent/JPS6089122A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5551100U (en) * | 1978-10-02 | 1980-04-03 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0463633B2 (en) | 1992-10-12 |
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