JPS6086873A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6086873A
JPS6086873A JP19414983A JP19414983A JPS6086873A JP S6086873 A JPS6086873 A JP S6086873A JP 19414983 A JP19414983 A JP 19414983A JP 19414983 A JP19414983 A JP 19414983A JP S6086873 A JPS6086873 A JP S6086873A
Authority
JP
Japan
Prior art keywords
schottky
layer
electrode
junction
ohmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19414983A
Other languages
Japanese (ja)
Inventor
Mutsuhiro Mori
睦宏 森
Masami Naito
正美 内藤
Yoshiteru Shimizu
清水 喜輝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19414983A priority Critical patent/JPS6086873A/en
Publication of JPS6086873A publication Critical patent/JPS6086873A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Abstract

PURPOSE:To produce a semiconductor device of larger space with high reliability by a method wherein electrodes forming Schottky junctions are discontinuously formed. CONSTITUTION:An n<+> layer, an n layer and a p<+> layer are formed on a semiconductor substrate 1. A schottky electrodes 30 are discontinuously formed partially coming into contact with the n layer. Besides, these Schottky electrode 30 are short-circuited by an anode electrode 22 coming into ohmic contact with the n layer. When the anode electrode 22 and a cathode electrode 21 are respectively supplied with minus and plus potentials, the current flowing through an ohmic junction 200 may be reduced by a depletion layer of a Schottky junctions 300 to block the supplied voltage. When said electrodes are supplied with reverse potentials, they are made conductive. Through these procedures, a semiconductor of larger space with high reliability may be produced.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置特にショットキ接合を有するダイ
オードに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, particularly a diode having a Schottky junction.

〔発明の背景〕[Background of the invention]

第1図は、ショットキ接合を有する半導体装置の1つで
ある従来のショットキダイオードを示している。纂1図
において、半導体基体1には、例えばn9型導電性の層
にn型導電性の層が隣接して形成されている。n層側の
主表面には、n層とショットキ接合を形成している電極
30が積層され、さらにアノード電極22が被着されて
いる。
FIG. 1 shows a conventional Schottky diode, which is one of the semiconductor devices having a Schottky junction. In FIG. 1, a semiconductor substrate 1 includes, for example, an n-type conductive layer adjacent to an n-9-type conductive layer. On the main surface on the n-layer side, an electrode 30 forming a Schottky junction with the n-layer is laminated, and an anode electrode 22 is further adhered.

40は810aなどの絶縁膜である。一般に、絶縁膜4
0とショットキ電極30の境界には、90層を設け、シ
ョットキ電極30の周辺部に県中する電界を緩和する構
造になっている。基体1のもう一方のn0側主表面には
、低抵抗で接触しているカソード電極21が形成されて
いる。
40 is an insulating film such as 810a. Generally, the insulating film 4
90 layers are provided at the boundary between Schottky electrode 30 and Schottky electrode 30, and the structure is such that the electric field distributed around the Schottky electrode 30 is relaxed. A cathode electrode 21 is formed on the other main surface on the n0 side of the base 1 and is in contact with the cathode electrode 21 with low resistance.

このようなショットキダイオードに熱疲労試験を加える
と、時間の経過とともに、逆電圧印加時の漏れ電流が増
大し、逆方向特性の劣化が生じる。
When such a Schottky diode is subjected to a thermal fatigue test, leakage current increases when a reverse voltage is applied over time, causing deterioration of reverse characteristics.

これは、熱疲労試験における冷熱ヒートサイクルによシ
、ショットキ電極30と半導体基体の1つである岡えば
シリコンの間の熱膨張係数の差に基づく熱応力や、また
この熱応力によりショットキ電極30の周辺部と5fO
s膜40の境界付近に応力の県中が生じる結果、界面単
位が増え、漏れ電流が増加したものと考えられる。熱疲
労試験をさらに続けると、クラックやはがれが生じる。
This is caused by thermal stress due to the difference in thermal expansion coefficient between the Schottky electrode 30 and silicon, which is one of the semiconductor substrates, and by this thermal stress, due to the cold heat cycle in the thermal fatigue test. peripheral area and 5fO
It is thought that as a result of the generation of stress in the vicinity of the boundary of the S film 40, the number of interface units increased and the leakage current increased. If the thermal fatigue test is continued further, cracks and peeling will occur.

このようなりラックやはがれを防ぐために、シリコンに
近い熱膨張係数を有する物質であるMOやWでショット
キ電極を構成する方法などが採られている。しかし、大
電流化するために、ショットキ電極の接合面積を増やす
と、この効果も充分′ではなく、高信頼のショットキダ
イオードを得ることができなかった。
In order to prevent such racking and peeling, a method has been adopted in which the Schottky electrode is made of MO or W, which is a substance having a coefficient of thermal expansion close to that of silicon. However, when increasing the junction area of the Schottky electrode in order to increase the current, this effect was not sufficient, and a highly reliable Schottky diode could not be obtained.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上述した従来の欠点を解決し信頼性の
向上を図ったショット接合を有する半導体装置提供する
ことである・ 〔発明の概要〕 本発明の特徴は、ショットキ接合を形成する電極を不連
続的に形成したことにある。
An object of the present invention is to provide a semiconductor device having a Schottky junction that solves the above-mentioned conventional drawbacks and improves reliability. [Summary of the Invention] The present invention is characterized by This is due to the fact that it was formed discontinuously.

〔発明の実施例〕[Embodiments of the invention]

第2図は、本発明の一実施例を示している。半導体基体
1には、n層層、n層% p”層が形成され、ショット
電極30は、部分的にn層に接触している。これらのシ
ョットキ電極は、n層にオーミック接触しているアノー
ド電極22によシ、短絡されている。アノード電極22
にマイナス電位、カソード電極21にプラス電位を加え
ると、ショットキ接合300の空乏層により、オーミッ
ク接合200を流れようとする電流を低減することがで
き、加えられた電圧を阻止することができる。
FIG. 2 shows an embodiment of the invention. On the semiconductor substrate 1, an n-layer and an n-%p'' layer are formed, and the Schottky electrode 30 is partially in contact with the n-layer.These Schottky electrodes are in ohmic contact with the n-layer. It is short-circuited by the anode electrode 22.Anode electrode 22
When a negative potential is applied to , and a positive potential is applied to cathode electrode 21 , the depletion layer of Schottky junction 300 can reduce the current flowing through ohmic junction 200 and block the applied voltage.

また逆に、アノード電極22にプラス電位、カソード電
極21にマイナス電位を加えると、オーミック接合20
0及びショットキ接合を流れ、導通状態となる。このよ
うな整流特性をもたせるには、ショットキ電極間の距離
りを側倒する必要がある。
Conversely, if a positive potential is applied to the anode electrode 22 and a negative potential is applied to the cathode electrode 21, the ohmic junction 20
0 and Schottky junction, and becomes conductive. In order to provide such rectification characteristics, it is necessary to increase the distance between the Schottky electrodes.

第3図に、整流特性を得るために必要な、距離りの好ま
しい範囲を示した。距離りは、n層のキャリア濃度及び
ショットキ接合の障壁の高さによシ異なるが、例えば、
n層のキャリア濃度3X1015鋸−3、障壁の高さ0
.9 Vでは、Lは1.2μm以下にする必要がある。
FIG. 3 shows the preferred distance range necessary to obtain rectifying characteristics. The distance varies depending on the carrier concentration of the n-layer and the barrier height of the Schottky junction, but for example,
Carrier concentration in n layer 3x1015-3, barrier height 0
.. At 9 V, L needs to be less than 1.2 μm.

第2図に示すような構造とし、例えばカソード電極にA
t1アノード電極にAu−8b、ショットキ電極にMO
を形成した場合、ショットキ接合で生じる歪を%Au−
8bなどの軟金属で構成できるオーミック電極で緩和す
ることができるため、熱疲労試験においてもクラックや
はがれ、漏れ電流の増大を防ぐことができた。その結果
、ショットキ接合面積を増やすことができ、従来60A
程度が限界であったショットキダイオードでも、200
A以上の電流を整流できる大面積の高信頼の素子を得る
ことができた。さらに、ショットキ電極には、f3iと
熱膨張率がほぼ等しいMOやWだけでなく、熱膨張率が
異なるP ’ # P d m N i*Crなどや、
さらには熱的安定性のあるTi5f2などの金属シリサ
イドを用いることもできる。これによシ、熱疲労試験に
強いショットキダイオードを得ることができるばかりで
なく、Mo(0,67V)やW(0,68V)以外の任
意のショットキ障壁の高さをもつショットキダイオード
を得ることができる。例えば、ショットキ金属にMgを
選ぶことによシ、障壁の高さを0.4vと低くし、順方
向の損失を少なくすることができる。一方、ptを用い
障壁の高さを0.9vとすることで、逆方向の漏れ電流
を少なくすることもできる。このように、本発明は用途
に応じた任意の金属を選択できるという長所もある。さ
らに、順方向の電流は、接触抵抗の低いオーミック接合
も流れるため、順方向の電圧降下が小さくなるという効
果もある。
The structure is as shown in Fig. 2, and for example, A
Au-8b for t1 anode electrode, MO for Schottky electrode
When forming a Schottky junction, the strain caused by %Au-
Since it can be relaxed with an ohmic electrode made of soft metal such as 8B, it was possible to prevent cracking, peeling, and increase in leakage current even in thermal fatigue tests. As a result, the Schottky junction area can be increased, and the conventional 60A
Even with Schottky diodes, which had a limit of 200
We were able to obtain a large-area, highly reliable element that can rectify a current of more than A. Furthermore, Schottky electrodes include not only MO and W, which have a coefficient of thermal expansion almost equal to f3i, but also P'# P d m N i *Cr, which has a different coefficient of thermal expansion, etc.
Furthermore, a thermally stable metal silicide such as Ti5f2 can also be used. As a result, it is possible not only to obtain a Schottky diode that is resistant to thermal fatigue tests, but also to obtain a Schottky diode having an arbitrary Schottky barrier height other than Mo (0.67 V) or W (0.68 V). I can do it. For example, by selecting Mg as the Schottky metal, the height of the barrier can be made as low as 0.4V, and forward loss can be reduced. On the other hand, by using PT and setting the height of the barrier to 0.9V, leakage current in the reverse direction can also be reduced. In this way, the present invention has the advantage that any metal can be selected depending on the application. Furthermore, since the forward current also flows through an ohmic junction with low contact resistance, there is an effect that the voltage drop in the forward direction is reduced.

第4図は、第2図のショットキ接合及びオーミック接合
を有する側の面の平面パターン図の一例である。ショッ
トキ接合300とオーミ・ツク接合200がストライブ
状に交互に並んでおシ、逆方向に印加した場合ショット
キ接合による空乏層によシ、オーミック接合を流れよう
とする電流を阻止することができる構造となっている。
FIG. 4 is an example of a planar pattern diagram of the side surface having the Schottky junction and ohmic junction in FIG. 2. When the Schottky junctions 300 and the ohmic junctions 200 are arranged alternately in a stripe pattern, and an electric current is applied in the opposite direction, the depletion layer formed by the Schottky junctions can block the current that attempts to flow through the ohmic junctions. It has a structure.

第5図は、他の平面パターン図である。ショットキ接合
300とオーミック接合200が基盤目状のわく内に交
互に配置されている。これにより、第4図でストライプ
状の長手方向に生じる歪をさらに減少することができ、
さらに大面積化に有利である。
FIG. 5 is another planar pattern diagram. Schottky junctions 300 and ohmic junctions 200 are alternately arranged within the grid-like frame. This makes it possible to further reduce the strain that occurs in the longitudinal direction of the striped shape in FIG.
Furthermore, it is advantageous for increasing the area.

第6図は、本発明の他の実施例である。第2図の実施例
と異なる点は、ショットキ接合300が、凹型に形成さ
れている点にある。これによシ、熱疲労試験に関する高
い信頼性を損うことなく、逆方向に電圧を加えた場合に
オーミック接合を流れようとする電流を、ショットキ接
合の空乏層により遮断する効果が強くなり、さらに逆方
向の漏れ電流を小さくできることが確認された。
FIG. 6 shows another embodiment of the invention. The difference from the embodiment shown in FIG. 2 is that the Schottky junction 300 is formed in a concave shape. As a result, the depletion layer of the Schottky junction becomes more effective in blocking the current that attempts to flow through the ohmic junction when a voltage is applied in the opposite direction, without sacrificing the high reliability associated with thermal fatigue tests. Furthermore, it was confirmed that the leakage current in the reverse direction could be reduced.

第7図は、オーミック接合領域K n ”層を設けた他
の実施例である。これによシ、さらに低抵抗のオーミッ
ク接合を得ることができ、損失が少なくなる。また、n
8層を形成したことによυ、高価なAu−8b電極の代
わ如に安価なAtを用いることができた。本実施例によ
り、低抵抗で安価なオーミック接合を形成した本発明の
ショットキダイオードを得ることができる。
FIG. 7 shows another embodiment in which an ohmic junction region K n '' layer is provided. This makes it possible to obtain an ohmic junction with an even lower resistance, resulting in less loss.
By forming eight layers, inexpensive At could be used instead of the expensive Au-8b electrode. According to this example, it is possible to obtain a Schottky diode of the present invention in which a low-resistance and inexpensive ohmic junction is formed.

本発明は、ショットキダイオードに限ることなく、ショ
ットキ接合を有する全ての半導体素子に適用可能である
The present invention is applicable not only to Schottky diodes but also to all semiconductor devices having Schottky junctions.

〔発明の効果〕〔Effect of the invention〕

以上、本発明によれば、大面積化が可能な高信頼の半導
体装置を得ることができる。
As described above, according to the present invention, a highly reliable semiconductor device that can have a large area can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のショットキダイオードの概略断面図、第
2図は本発明のショットキダイオードの概略断面図、第
3図はショットキ電極間の距離とn層のキャリア濃度の
関係を示す図、第4図及び第5図はショットキ接合、オ
ーミック接合面の平面パターン図、第6図及び第7図は
本発明の他の実施例を示す概略断面図である。 第1図 も2日 翳3図 一/−3ットN電下ト間。正高圧、[伊罰牢6日 もq図
FIG. 1 is a schematic sectional view of a conventional Schottky diode, FIG. 2 is a schematic sectional view of a Schottky diode of the present invention, FIG. 3 is a diagram showing the relationship between the distance between Schottky electrodes and the carrier concentration of the n-layer, and FIG. 5 and 5 are planar pattern diagrams of a Schottky junction and an ohmic junction surface, and FIGS. 6 and 7 are schematic sectional views showing other embodiments of the present invention. Figure 1 is also between 2 days and 3 figures 1/-3t N electric bottom. Positive high pressure, [Ipaku Prison 6th also q figure

Claims (1)

【特許請求の範囲】[Claims] 1、一方の主表面に一方導電型の層が露出する半導体基
体と、一方の主表面にショットキ接合を形成する如く設
けられた第1の電極と、第1の電極から離れて半導体基
体にオーミック接触した第2の電極とを備え、上記ショ
ットキ接合が不連続的に形成されていることを特徴とす
る半導体装置。
1. A semiconductor substrate in which a layer of one conductivity type is exposed on one main surface, a first electrode provided on one main surface to form a Schottky junction, and an ohmic layer separated from the first electrode and attached to the semiconductor substrate. A semiconductor device comprising a second electrode in contact with the Schottky junction, the Schottky junction being formed discontinuously.
JP19414983A 1983-10-19 1983-10-19 Semiconductor device Pending JPS6086873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19414983A JPS6086873A (en) 1983-10-19 1983-10-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19414983A JPS6086873A (en) 1983-10-19 1983-10-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6086873A true JPS6086873A (en) 1985-05-16

Family

ID=16319726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19414983A Pending JPS6086873A (en) 1983-10-19 1983-10-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6086873A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506450A2 (en) * 1991-03-28 1992-09-30 Murata Manufacturing Co., Ltd. A Schottky barrier diode and a method of manufacturing thereof
EP2320466A1 (en) * 2008-08-21 2011-05-11 Showa Denko K.K. Semiconductor device and semiconductor device manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506450A2 (en) * 1991-03-28 1992-09-30 Murata Manufacturing Co., Ltd. A Schottky barrier diode and a method of manufacturing thereof
EP0506450A3 (en) * 1991-03-28 1994-08-24 Murata Manufacturing Co A schottky barrier diode and a method of manufacturing thereof
EP2320466A1 (en) * 2008-08-21 2011-05-11 Showa Denko K.K. Semiconductor device and semiconductor device manufacturing method
EP2320466A4 (en) * 2008-08-21 2013-12-11 Showa Denko Kk Semiconductor device and semiconductor device manufacturing method
US9035321B2 (en) 2008-08-21 2015-05-19 Showa Denko K.K. Semiconductor device and manufacturing method of semiconductor device

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