JPS6086869A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To equalize the gate cut-off voltage by a method wherein an n<+> conductive layer at high concentration to be source and drain part near a gate electrode is selfmatchingly formed with high precision and excellent reproducibility without diffusing a gate metal in an operating layer. CONSTITUTION:A plasma silicon nitride film 23 as a protecting film is grown on a high resistance GaAs substrate 4 implanting Si<+> ion therethrough to form an N type opening layer 5. A silicon oxide film 21 is evaporated and another plasma silicon nitride film 22 is grown to form a pattern covering the peripheral part of the pattern 22 and the N type opening layer 5 to be a gate part on said layer 5. Firstly the film 21 is etched to form the gate pattern 21 further forming a high concentration conductive layer 6 by ion implanting process. Secondly overall surface is covered with a plasma nitride film 24 and after coating and drying up a photoresist film 26, overall surface is etched and the residual photoresist film 26 is removed to form electrodes 1-3. In such a constitution, gate metal may be prevented from diffusing in the operating layer as well as the gate Schottky characteristics from deteriorating to equalize the gate cut-off voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a Schottky barrier gate type field effect transistor, and more particularly to a method for manufacturing a field effect transistor in which the distances between the gate part and the source and drain/parts are shortened and formed in a self-aligned manner. Regarding.

GaAs semiconductors have an electron mobility that is 5 to 6 times higher than that of 8i, and because of this high speed characteristic, research and development for application to ultrahigh-speed integrated circuits (ICs) has been conducted in recent years. It is actively carried out. The active element of this GaA sIC is basically a Schottky barrier field effect transistor (ME8FET) as shown in Figure 1.
) has been proposed. This is called a planar structure, and an active layer 5 made of n-type impurities with a thickness of approximately 0.2 μm is formed on a semi-insulating GaAs substrate 4 by epitaxial growth or ion implantation, and then lift-off is performed using a photoresist film. It has a relatively simple structure, in which a gate electrode 1 is formed by a method or the like, a mask is aligned, and ohmic electrodes 2 and 3 for the source and drain are formed by a similar lift-off method or the like.

However, such a method of manufacturing a planar structure requires alignment in order to form an ohmic electrode. The alignment accuracy is about ±0.5 μm even in the best equipment, and about ±1.0 μm in practical machines. In ME8FET manufactured using such an alignment device, it is actually difficult to reduce the electrode distance between the ohmic electrode and the gate electrode to 1.0 μm or less. On the other hand, G between the gate electrodes
On the surface of the aAg active layer, as shown in Figure 2, a surface depletion layer 9 is generated due to disturbance of crystallinity on the surface, adsorption of gas, etc., and the effective active layer becomes thin. If the distance between the electrodes is long, the active layer resistance between the gate and the source (source series resistance) increases and the mutual conductance gm decreases significantly, making it difficult to obtain good FBT characteristics.

Therefore, various methods have been proposed to avoid the alignment problem and reduce the source series resistance. FIG. 3 shows what is called a recessed structure, in which the active layer 5 is formed thickly, the gate portion is dug using photoresist or the like as a mask, and the gate electrode 1 is formed in a self-aligned manner by a lift-off method or the like.

This structure reduces the source series resistance by thickening the active layer outside the vicinity of the gate. However, since the gate portion is etched by wet etching, the gate cut-off voltage V7- of the KFET varies considerably, which is not desirable for highly integrated circuits. FIG. 4 shows what is called a short interelectrode structure, in which an AI gate electrode 1 is formed by side etching using a photoresist as a mask, and an ohmic electrode AuGe 2.
3 is formed in a self-aligning manner by lift-off. Although this structure allows the electrode spacing to be narrowed to 0.4 .mu.m, it has the drawback that it is difficult to achieve accuracy below this.

In FIG. 5, an n-chiroelectric layer 6 in which n-type impurities are ion-implanted at a high concentration is provided under the ohmic electrodes 2 and 3 so as to be close to the gate electrode 1. However, since the n-chihiro conductive layer 6 itself is formed in large numbers by re-alignment, the influence of the surface depletion layer is the same as in FIG. 1, and this is not practical for highly integrated circuits.

In Figure 6, after forming an n-type active layer 5, ions are implanted using a highly heat-resistant gate electrode l as a mask to form an n-chihiro conductive layer 6 in a self-aligned manner, and an ohmic electrode 2°3 is provided. It is. With this structure, it is difficult to microfabricate the highly heat-resistant GaAs gate electrode 1. Also, after ion implantation of the n-chihiro conductive layer 6, heat treatment at about 800°C is required to recover crystallinity. 1 diffuses into the n-type active layer 5, resulting in poor key characteristics and gate cut-off voltage V being susceptible to change.

FIGS. 7(a) to (r) show the formation of an n-chihiro conductive layer as an application of FIG. 4 without using a highly heat-resistant gate metal.

As shown in (,), an n-type active layer 5 is formed on a semi-insulating GaAs substrate 4, and as shown in (b), a plasma nitride film of 0.15 μm 1 is applied as a protective film 12, followed by a high heat-resistant resist 11.
Sputter-deposited oxide film 13 of 0.8 μm thick is coated on the entire surface with a thickness of 0.3 μm, and using photoresist as a mask, parallel plate dry etching is performed to etch sputter-deposited oxide film 11 (high heat resistance regime) using CF4+AT gas to form ohmic parts. After that, the remaining oxide film 13 was used as a mask to perform cylindrical dry etching using oxygen gas, and the highly heat-resistant resist 11 was side-etched several thousand times. A conductive layer 6 is formed by ion implantation through the nitride protective film, and the sputter-deposited oxide film 14 has a thickness of 0.0 mm as shown in (C).
When the entire surface is covered with a thickness of 3 μm and etched with a back-atto hydrofluoric acid solution as shown in (d), the sputter-deposited oxide film 14 attached to the side wall of the high heat resistant resist 11 is weak and melts quickly, causing the high heat resistant resist to disappear. When it is dissolved in a comb solution and lifted on, a gate opening 15 that becomes a gate portion is created, and by heat treatment using the plasma nitride film 12 as a protective film, the crystallinity of the operating layer 5 and the n-chiroelectric layer 6 is restored. (C)
As shown in (f), the plasma nitride film 15 is etched using the oxidized film 14 as a mask by cylindrical dry etching to expose the active layer 5, and the gate opening 15 is opened as shown in (f).
The ME8FET is completed by forming an overlay gate electrode 1 on top and forming source and drain ohmic electrodes 2 and 3 on the n-chihiro conductive layer 6. In this manufacturing method, the gate metal electrode is formed after the ion-implanted layer is heat-treated, so there is no problem of the gate metal diffusing into the active layer. However, the problem with this manufacturing method is that the sputter-deposited oxide film attached to the highly heat-resistant resist has weak crystallinity and is dissolved in buffered hydrofluoric acid to lift off the gate opening 1.
However, wet etching using such selectivity as the shape accuracy required by the FIT characteristic has poor reproducibility and processing accuracy, and is not suitable for stable mass production.

The accuracy of the gate opening 15 is n in the case of protective film ion implantation.
In order to prevent the high carrier concentration on the surface of the Chihiro conductive layer from deteriorating the drain withstand voltage and FET saturation characteristics, the highly heat-resistant resist 11 is side-etched several thousand times using the oxide film 13 as a mask. The accuracy of the aperture 15 needs to be less than this.

However, in wet etching that takes advantage of the selectivity of crystalline materials, if the etching time is shortened in order to make the gate opening more precise, some areas may not be lifted off.
If the etching time is increased in order to ensure lift-off, the gate opening will widen, the final gate length will become longer, and problems such as drain withstand voltage and drain conductance will decrease. Furthermore, the boundaries of the crystalline film at the corners of the sputter-deposited oxide film are in the direction of microcracks, and the walls of the etched gate openings 15 are not vertical but oblique. When the underlying plasma nitride film is isotropically etched by cylindrical dry etching using the gate opening of this oxide film as a mask, the oxide film itself is etched and spread, and the gate opening of the plasma nitride film becomes wider. Furthermore, if the etching time is increased in an attempt to ensure that no plasma nitride film remains in the gate opening, side etching occurs and the gate opening becomes wider.

As described above, as the process progresses, the gate opening becomes wider and at the same time the variation in gate length becomes larger. As a result, the final FIT4I properties have large fluctuations, and even if this manufacturing method is applied to highly integrated circuits, the desired good circuit characteristics cannot be obtained due to poor matching of device characteristics. .

The purpose of the present invention is to obtain a good MFt8FET that is free from the influence of the surface depletion layer and has a uniform gate cut-off voltage.
Provided is a method for manufacturing a field effect transistor in which gate metal does not diffuse during operation and a highly concentrated n-chihiro conductive layer that becomes the source and drain parts is formed in a self-aligned manner with high precision and reproducibility up to the vicinity of the gate electrode. It's about doing.

According to the present invention, a step of forming an impurity layer that becomes a field effect transistor portion and a protective film covering the surface on a semiconductor substrate, and forming a first pattern and a first pattern on the protective film of the impurity layer to determine the shape of the gate. a step of stacking and forming a second pattern having a larger area than the first pattern on the first pattern; and a step of forming a highly concentrated impurity in the impurity layer by ion implantation using the second pattern as a mask. a step of restoring the crystallinity of the high concentration impurity layer by heat treatment; a step of covering the entire surface with a coating film and removing the coating film above the first pattern; a step of removing the first pattern to form an opening in the covering film; a step of removing the protective film under the opening of the covering film to expose the impurity layer to form a gate opening; A method for manufacturing a field effect transistor is obtained, which includes a step of forming a gate electrode.

Next, the present invention will be explained using examples. Figure 8(a)-(
h) is a diagram illustrating the manufacturing process of the present invention.

As shown in (a), a plasma silicon nitride film 23 is grown to a thickness of 0.1 μm over the entire surface of the high-resistance GaAs substrate 4 as a protective film, and S1 ions are accelerated at a voltage of 100 KeV through the plasma nitride film 23 using a photoresist pattern as a mask.
Ion implantation was performed at a dose of 3.2 x 10"tX-".
After forming a functional layer 5, a silicon oxide film 2 is formed as shown in (b).
1 is sputter-deposited to a thickness of 0.6 μm, a plasma silicon nitride film 22 is grown again to a thickness of 0.3 μm, and a parallel electrode type dry etching is performed using CF and gas using the photoresist pattern as a mask to form an n-type active layer. A pattern 22 with a gate length of 1.5 μm which will become a gate part and a pattern covering the peripheral part of the n-type operating layer 5 are formed on the buffered hydrofluoric acid made of ammonium fluoride water as shown in (C). The oxide film 21 under the liquid plasma nitride film 22 is heated to 25 μm.
M side etching is performed to form an oxide film gate pattern 21 with a gate length of 1.0 μm, and as shown in (d), 8i+ ions are accelerated at a voltage of 18 using the plasma nitride film 22 as a mask.
A highly concentrated conductive layer 6 was formed by ion implantation at 0 KeV and a dose of 7 x 10"aa-", and heated at 800°C2 in hydrogen.
The crystallinity of the active layer 5 and the high concentration conductive layer 6 is restored by heat treatment for 0 minutes, and the coating film is formed into a coating film with a thickness of 0.0 minutes as shown in (e).
The entire surface is covered with a plasma nitride film 24 of 6 μm, and a photoresist film 26 is applied to a thickness of i, 0 μm and dried at 180° C. for 30 minutes. The surface of the photoresist film 26 becomes smooth, and the photoresist film 26 on the gate pattern 21 becomes thinner. ,C1(
As shown in r), the entire surface is etched by parallel electrode type dry etching using CF4 gas to expose the gate pattern 21 of the oxide film, and as shown in ω, the remaining photoresist film 26 is removed with a stripping solution, and then buffered. When the gate pattern 21 of the oxide film is selectively etched away using a hydrofluoric acid solution, a gate opening 25 remains in the plasma nitride film 24.
Using the plasma nitride film 24 as a mask, the plasma nitride film 24 under the gate opening 25 is vertically etched to expose the GaAs surface, and then heat treated in H2 at 450° C. for 30 minutes. After recovering the damage, as shown in (h), a double aluminum body is deposited on the entire surface and etched using a photoresist pattern as a mask to form an aluminum gate electrode 1.
Using the photoresist pattern with an opening on the high concentration conductive layer 6 as a mask, the plasma nitride film 23, 24 is removed by etching, ohmic metal AuGe-Pt is deposited, the photoresist pattern t is melted and lifted off, and the etching is performed in hydrogen for 480°C.
By diffusing AuGe into the high-concentration conductive layer 6 by heat treatment for 5 minutes at °C, source and drain ohmic electrodes 2 and 3 are formed, completing a GaAs ME'5FET.

The etching rate of the plasma nitride film by the back-atto hydrofluoric acid solution is 1/20 or less of that of the oxide film, so changes in the shape of the plasma nitride film do not pose a problem. Furthermore, the uniformity of side etching of the silicon oxide film using the back-atto hydrofluoric acid solution is good, and the amount of etching can be controlled by the etching time.

In the embodiment, a silicon oxide film is used for the gate pattern 21, a plasma nitride film is used for the storage film 23, the n+ injection mask 22, and the coating film 24, but the present invention is not limited to this. Storage membrane 2
3 may be any material that does not react with GaAs during heat treatment at 800°C, such as oxides such as aluminum oxide, -silicon oxide, silicon dioxide, and titanium oxide, aluminum nitride, silicon nitride, boron nitride, and gallium nitride. Nitride of may also be used. The gate pattern 21 may be made of titanium, molybdenum, titanium, molybdenum, etc. in addition to insulating films such as oxides and nitrides.
High melting point metals such as tungsten and tantalum may also be used. Since the n+ implantation mask 22 may be removed before heat treatment at 800° C., a metal or organic resin may be used instead of an insulating film such as an oxide or nitride.

In addition, the upper part of the covering film 24 is removed to form the gate pattern 21.
Although the entire surface was etched by applying a resist to expose it, it may also be exposed by polishing.

Furthermore, although the present invention has been described as a method for manufacturing a Schottky barrier gate type FIT, p-type impurities such as Be, Mg, and Zn are ion-implanted or diffused into the n-type active layer 5 from the gate opening 25 to form a gate portion. It may be a junction gate type FET using a pn junction.

According to the present invention as described above, the initially formed gate pattern with vertical walls is converted into an inverted shape as a gate opening in the coating film, and heat treatment is performed to restore crystallinity while maintaining the gate with vertical walls. By filling this gate opening with gate metal again, it is possible to reproduce the same gate shape as the gate pattern.

Since the gate length of the gate electrode is determined by the initially formed gate pattern, it is possible to stably produce MB8FETs with good Schottky characteristics and FFtT characteristics with good reproducibility. Then, in order to form the gate electrode after heat treatment to recover the crystal, the gate metal is diffused into the active layer.
Gate cutoff voltage vT with poor gate Schottky characteristics
There will be no problem such as a large variation due to fluctuations.

The gate metal does not need to be highly heat resistant, and common materials such as aluminum, titanium, and chromium can be used.

The characteristics of the MESFET of this embodiment in which the source and drain portions are formed in a self-aligned manner with respect to the gate electrode are as follows: When the gate width is 10 μm and the gate length is 1.0 μm, the gate cutoff voltage VT is the average value +〇, 094 V. Good results were obtained with a standard deviation of 0.084 V and a mutual conductance gm of 2.6 mS. In a conventional short electrode structure with a gate width of 10 μm and a gate length of 1.0 μm as shown in FIG. 4, gm is 0.8 mS, and in a structure with aligned electrode spacing of 1.5 μm as shown in FIG. is 0.2
In some cases, the drain current was less than m8 and no drain current flowed at all. As described above, the effects of the present invention are clear from the comparison with the characteristics of the conventional MFi8FET.

[Brief explanation of the drawing]

Figure 1 shows a conventional Schottky barrier gate field effect transistor (MBSFET) with the most basic planar structure.
), and Figure 2 is a cross-sectional view of this planar structure MES.
This figure shows a state in which a surface depletion layer is generated on the surface of the GaAs active layer of the FET. Figure 3 shows an MBSFET with a recessed structure in which the gate portion is dug, Figure 4 shows an MESFET with a short inter-electrode structure in which the source and drain metal electrodes are brought close to the gate electrode, and Figure 5 shows an MBSFET with a recessed structure in which the gate part is dug. Figure 6 shows an MBSFET with a planar structure that has an n-chihiro conductive layer. f) is a diagram illustrating a method of manufacturing a MESFET in which an n-chihiro conductive layer is provided by applying FIG. 4 without using a highly heat-resistant gate metal. FIGS. 8(a) to 8(h) are diagrams for explaining the manufacturing method of the present invention. In the figure, 1 is a gate electrode, 2 is a source electrode, 3 is a drain electrode, 4 is a high resistance GaAs substrate, 5 is an n-type operating layer, 6 is a high concentration conductive layer, 9 is a surface depletion layer, and 11 is a High heat resistant resist, 12 plasma nitride film, 13.14 sputter deposited oxide film, 15 gate opening, 21 gate pattern, 22 ion implantation mask for high concentration conductive layer, 23
24 is a protective film, 24 is a coating film, 25 is a gate opening, and 26 is a resist. 71-1 Figure 4 Figure 7 Figure (a) (d) 1-8 Box (b) (C) (e) (f) (9)

Claims (1)

[Claims] A process of forming an impurity layer that will become a field effect transistor part and a protective film covering the surface on a semiconductor substrate, and forming a first pattern on a holding film for the impurity layer to determine a gate shape, and a process based on the first pattern. a step of stacking and forming a second pattern with a large area on the first pattern; a step of forming a highly concentrated impurity layer in the impurity layer by ion implantation using the second pattern as a mask; a step of restoring the crystallinity of the high concentration impurity layer by heat treatment, a step of removing the covering film on the upper part of the first pattern whose entire surface is covered with a loose covering film, and a step of removing the first pattern. forming an opening in the covering film; removing the protective film under the opening of the covering film to expose the impurity layer to form a gate opening; and forming a gate electrode in the gate opening. A method for manufacturing a field effect transistor, comprising: