JPS6086827A - Electron beam exposure method - Google Patents

Abstract

PURPOSE:To reduce the exclusive area of a chip mark by forming the rectangular chip mark having long sides parallel with an axis of arrangement of a scribing line. CONSTITUTION:Rectangular chip marks 14 having long sides parallel with axes of arrangement of scribing lines are formed in regions in the vicinity of each chip corner 13a, 13b, 13c, 13d on scribing lines 12y, 12x demarcating a chip region 11 on a semiconductor substrate to be treated. Chip marks 15, 16 to other chip regions and other adjacent chip regions are also formed adjacently in series. These marks are scanned by electron beams in the directions rectangular to the long sides and the central coordinates of each chip mark on scanning lines are detected, drawing exposure regions are determined while using the positions of quadrilaterals formed by tying these central coordinates as references, and several layer pattern is drawn and exposed. Accordingly, the exclusive areas of chip positioning marks disposed on the scribing lines can be reduced, and areas capable of being used for applications other than the scribing lines can be increased.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an electron beam exposure method. ◎ (b) Regarding the method of positioning the chip area in the exposure method: Background of the technology The direct pattern writing method using a sub-beam has high resolution and alignment function, so it is the most powerful method in the manufacturing process of submicron devices. 〇On the other hand, in recent years, there has been a growing trend towards small-volume, high-variety device lifecycles, and this direct writing technology, which does not require a mask, will reduce manufacturing costs and increase production time. ◎Recently, the speed of technology development in the semiconductor industry has been accelerating, and under these circumstances, it has been shown that it has a great effect on shortening the development and prototyping period for each device. The technique has been used successfully.

(c) Conventional technology and problems In the above-mentioned direct writing method using an electron beam.

A specific mark consisting of a concave or convex portion is provided on a substrate to be ripened, for example, a semiconductor substrate to be processed, and by detecting the mark with an electron beam, several layers are toned using the mark as a reference.
The lf4 patterns are drawn in an overlapping manner. In the general case where the chip size is smaller than the scanning field of the electron beam, marks (chip marks) are provided at the four corners of the chip area, and the positions of these marks are detected by scanning the electron beam. The accurate position and shape of the chip area is determined based on the rotational error (1) positional error, elongation (0) trapezoidal error, etc., which can be seen from the data, and the deflection of the electron beam is corrected based on this to determine the accurate position of the chip area. A pattern is drawn. The method of providing chip marks at the four corners of the chip area is called the four-point mark method. In addition to this, there is also a method in which chip marks are provided at three corners of the chip area, but the exposure operation in this method is the same as in the four-point mark method.

For example, in the four-point mark method described above, a chip mark consisting of a square concave portion is generally used.

In this case, it is difficult to expose multiple layers using one or a set of chip marks at each corner. From the sun 1O~2
Since scanning is repeated approximately 0 times in the X and Y directions, the positive resist film formed in the scanning area becomes negative due to extremely excessive exposure, and when the positive resist film is developed after pattern drawing is completed. .

The negative areas are not removed. Therefore, when patterning, for example, an oxide film using the resist film as a mask, the oxide film remains on the chip mark where the negative resist film remained, and the chip mark is deformed. This state is schematically shown in the top view of Figure 1 (A) and the top view of Figure 1 (A).
This is a sectional view taken along the line A-A in Figure (0), and 1 in the figure is a semiconductor substrate;
2 is a chip mark, 3 is an oxide film, and sx and sy are scanning direction arrows.

When a multilayer pattern is drawn and exposed, the chip marks are deformed one after another, making it impossible to accurately detect the chip mark position. For this reason, conventionally, as schematically shown in FIG. 2, the number of chip marks corresponding to the number of layers to be exposed is 2al+2at+2 when exposing 6 layers, for example.
as+ 2a++ 2al+ 28@+ 2J +2J
r 2bs + 2ba * 2ba + 2ba
r 2 e 1 t 2 e! e 20 a+2c4+
2cs* 2ca* 2d+* 2dt+ 2ds+
2d4 + 2ds + 2d6 are arranged side by side on the scribe line 6 near the corner portions 5a + 5b *5c and 5d of the chip area 4, and for example 2al is arranged every 5 layers.
+ 2 b I + zc, za, - set of chip marks or 28 @ + 2 b I + 2 e
* A set of chip marks consisting of +2 ds is scanned in the X and Y directions by an electron beam, and each -
The exact position of the chip area 4 was determined by detecting the center position of a set of chip marks.

However, in such conventional methods, the beam scanning for detecting the position of each chip mark is also performed in the direction in which the chip marks are lined up. It is necessary to allow for an extra dimension so that the traces on the upper surface of the resist film caused by the beam scanning do not affect the detection of adjacent chip marks. Therefore, the interval between the chip marks becomes wider and the chip mark occupies the scribe line. The length is very large. - For example, a chip mark of 15 [μm] square is 6
In the case of layer exposure, the amplitude of the beam is about 40 [μm], the margin dimension is about 10 [μm], and the length that the chip mark occupies the scribe line is about 0.3 [μm].

The scribe line is also used as an area for placing alignment marks for various monitor patterns and projection exposure using the step-and-repeat method, so chip marks do not occupy a large area as described above. , there was a problem that caused problems with the manufacturing staff of the semiconductor device.

(d) Purpose of the Invention In view of the above-mentioned problems, the present invention reduces the area occupied by chip marks on the scribe line when patterns are drawn in multiple layers using an electron beam, and provides other uses for the scribe line. (e) Structure of the Invention That is, the present invention is an electron beam exposure method in which a plurality of areas are defined and arranged by scribe lines on a substrate to be processed. At least three or more corners of the chip area are defined during electron beam exposure in which multiple layers of patterns are directly drawn in a stacked manner based on the chip marks arranged for each chip area on the chip area. A rectangular chip mark having a long side parallel to the cast axis of the scribe line is provided on the area near the corner of each of the two scribe lines, and a rectangular chip mark is placed on each rectangular chip mark for each pattern drawing layer. C, characterized in that the chip area is positioned by scanning different locations with an electron beam in a direction across the long sides of each chip mark and detecting the coordinate position of the chip mark on the scanning line. A) is a schematic top view of one embodiment showing the shape and arrangement of chip marks used for water droplets of the present invention.

Figure 3 (middle) is a partially enlarged view of the same. 〇When exposing multiple layers on the same substrate using the direct exposure method using an electron beam of the present invention, for example, as shown in Figure 3 (a), A scribe line 12F++1 defining a chip area 11 on a semiconductor substrate to be processed as shown in FIG.
2. X++ 123'! In the vicinity of each chip corner L3a, 13b, 13c, L3d on l l 2xt, a rectangular chip mark 14 a y+ L 4 a having a long side parallel to the axis of arrangement of the scribe line.
x r, Ic1 14 b 'l, l 4 b x + L 4 c
y, 14 c x + 14 g F + L 4 t
15 is another chip area, and 16 is a chip mark for another adjacent chip area @The pattern arrangement on the substrate is the chip area 11 and the chip mark 14ay.

14ax, t4by, 14bx, 14cy+L4cx+
t4ay.

In the exposure method of the present invention, which is performed by a step-and-repeat method using a reticle equipped with L4dx, the chip area 11
Rectangular chip marks 14a7.14ax*14b7.14bx are formed on the scribe line so as to sandwich each corner portion 13a, 13b, 13c, 13d.

14cy, 14cx*L4dy, 14dx are scanned by an electron beam in a direction approximately perpendicular to the long sides, the center coordinates of each chip mark on the scanning line are detected, and the position of the quadrilateral formed by connecting these center coordinates is determined. The drawing exposure area is determined based on the reference, and the drawing exposure of each layer pattern is performed.In the method of the present invention, the exposure area is determined by the above procedure, so the center position of the chip mark is detected. As mentioned above, the electron beam can be scanned in only one direction that intersects (usually intersects at right angles to) the scribe line on which the chip mark is arranged. By forming the chip in a rectangular shape with long sides parallel to the axis of the scribe line to be exposed, the area deformed by beam scanning when exposing one chipmer IC lower layer pattern can be avoided, and the chip can be easily removed when exposing the next layer pattern. It becomes possible to detect the exact position of the mark.

FIG. 3 is a partially enlarged view showing an example of beam scanning when detecting the chip mark position, and 11 in the figure is a chip area -14.
ay, L4ax are chip marks % for the chip area 11, 16 are chip marks of other adjacent chip areas (not shown), S XI, S Yt.

SXz, SYt, SXs, 5Y3-5X4- SY4
．． SXI-8'Y+, SXa, and SYa are arrows indicating beam scanning when positioning the first, second, third, fourth, fifth, and sixth layers, respectively.

In this way, in the present invention, since the beam scanning of each layer on the same chip mark is only in parallel directions, it is difficult to detect the position in the beam scanning when the chip mark is deformed due to the beam scanning. For example, when using an ordinary electron beam of about 1.0 [μm] square, a beam spacing of about 14 (μm) is sufficient to avoid any influence.

Therefore, when exposing 6 layers as in the conventional example, the length of one chip mark required is approximately 98 [μm], and in the method of the present invention, each chip corner is Since chip marks on two sides are required, the total length is a little less than 0.2 (m).In this way, in the case of 6 layers, the length of the chip mark occupying the scribe line is the same as the conventional length of 0.2 (m).
It is reduced to about 1 compared to about 3 (m), but if the number of layers is further increased, the reduction rate will further increase, and for example, with 12 layers, it can be reduced to near the top (g) Invention As described in detail, the present invention makes it possible to reduce the exclusive area of the chip alignment mark placed on the scribe line when drawing a multilayer pattern in a convergent manner using the direct path light of an electron beam. Therefore, the present invention is effective in the manufacturing process of semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a top view (A) and a sectional view taken along the line A-A (0) showing the shape and problems of a conventional chip mark, and FIG. 2 is a schematic top view showing the arrangement of the conventional chip mark. FIG. 3 is a schematic top view (a) and a partially enlarged view (b) of an example showing the shape and arrangement of chip marks used in the method of the present invention. In the figure, 11 is a chip area, l 2y*+ 12Xx
et zy,, 12x is the scribe line, 13a
*13b*L3c, 13d are chip corners, ■B y
, l 4 a x *14b)' m 14 bx
* 14c 'Is 14 cx* L 4dye L
4dx is chip mark, SXs, 5Yt-SXt, 5
Yt-5Xs-8YI-8X4.8Y4.8X8. S.Y.
g, 5Xa-8Ye indicate the beam scanning direction arrow.

Claims (1)

[Claims] Electron beam exposure in which patterns of several layers are directly drawn on a plurality of chip areas defined and arranged by scribe lines on the substrate a to be processed, overlapping each other based on the chip marks arranged for each chip area. In this case, a rectangular chip having a long side parallel to the cast axis of the scribe line is placed on each of the two scribe lines that define each of the at least three corners of the chip area in the vicinity of the corner. By providing a mark, scanning different locations on each rectangular chip mark for each layer of pattern drawing with an electron beam in a direction across the long side of each chip mark, and detecting the coordinate position of the chip mark on the scanning line. An electron beam exposure method characterized by positioning a chip area.