JPH01215022A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a wiring with a high accuracy and a high degree of freedom by sensing the position of the wiring between independently manufactured semiconductor integrated circuit regions and drawing a wiring pattern between the semiconductor integrated circuit regions through beam scanning on the basis of the quantity of pattern shift corresponding to the displacement of the position. CONSTITUTION:A position is sensed by scanning the upper sections of each alignment mark 10, 11 by beams before a wiring pattern is manufactured, and the quantity of pattern shift 12 to an X region of a Y region is measured. A wiring 9 is divided into a wiring 13 belonging to the X region, a wiring 14 belonging to a boundary region between both the X and Y regions and a wiring 15 belonging to the Y region, the divided wirings 13, 41 are drawn, using the alignment mark 10 in the X region as a reference, and the wiring 15 is drawn, employing the alignment mark 11 in the Y region as a reference. Lastly, a correction pattern 16 is manufactured on the basis of the quantity of pattern shift 12 to the X region of the Y region which is measured previously and exposed, and mutually displaced X-region wiring hole 6 and Y-region wiring hole 8 are wired.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular! t'
9 of the large-scale IA1f4 circuit devices that cover the entire surface of the four-piece wafer! ! ! ! It is related to the manufacturing method.

[Conventional technology]

Semiconductor FFI product circuits are becoming larger in size year by year, and
It is not uncommon for chips to have a chip size of 20 mm square.

However, in order to obtain a large-scale integrated circuit device with more functions, a semiconductor wafer of 1 a1 (about 70 m in diameter)
Attempts have been made to reduce the number of chips (m to 150 mm) into one integrated circuit chip. This is a wafer scale integration method.
It is called 5cale Integration (WSI).

In order to fabricate a semiconductor U4 circuit device over the entire surface of a wafer, it is common to print the circuit using a semiconductor mask of the same size as the wafer. Microfabrication with an accuracy of 2 μm or less is difficult due to various factors in the process of manufacturing the device (for example, warping of the studs, etc.). Therefore, in order to increase the height to 145M, IL! Individual semiconductor integration even if the I omitted is burned in! Since the single-path device is large, there is a problem in that the degree of integration as a circuit cannot be increased.

Currently, microfabrication of 1 μm or less is carried out using a device called ``Sute Soba.'' This device divides the wafer into smaller areas and prints circuits without aligning each area. , which has the advantage of being able to perform microfabrication with high precision.

[Problem to be solved by the invention]

However, when performing wafer scale intergray 1 using a device called a stepper, as shown in FIG. The wiring holes (A, B, C, . . . H, respectively) must be interconnected. For example, if the mutual positions of region A and region B within the wafer surface do not deviate from the designed position, Cζ is not shown in FIG. 4(a). can be connected by, but the fourth
As shown in Figure (b), if the wiring holes 5 are misaligned, connection cannot be made with the wiring 4 according to the design.

In the above, the problem was the wiring between areas A and 8 in FIG. 3, but since the positional deviation from area A to the faster area [1 is large, the situation worsens.

This invention was made in view of the above points, and enables mutual wiring even when there is a positional shift between regions due to the use of a lithography device such as an electron beam, focused ion beam, or laser beam. It is an object of the present invention to provide a method for manufacturing a semiconductor device manufactured using an inch-gray scale.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention is a method for wiring between semiconductor integrated circuit regions independently manufactured on a semiconductor ware, using alignment marks created in each semiconductor integrated circuit region. The position of the wiring area is detected, the positional displacement of the wiring position between the semiconductor integrated circuit areas is detected, and the wiring pattern is drawn by beam scanning while correcting the amount of pattern shift according to the positional displacement.

[Effect]

In this invention, the wiring positions between semiconductor integrated circuit regions independently fabricated on a semiconductor wafer are detected, and if there is a positional displacement in this wiring position, the positional displacement is detected, and the positional displacement is detected. Since the wiring pattern is drawn between the semiconductor integrated circuit regions by beam scanning based on the corresponding pattern shift amount, wiring can be performed with a high degree of freedom for any positional displacement.

[Example] Hereinafter, an example of the invention of Party B will be described with reference to the drawings. In FIG. 1(a), the X area to the left of the broken line 1117 and the Y area to the right of the broken line 18 are areas that are independently patterned using a stepper. Now, consider connecting the wiring hole 6 in the X area and the wiring hole 7 in the Y area by a wiring 9. X
A relative positional shift occurs between the area and the Y area,
If the wiring hole 7 has moved from its intended position to the position of the wiring hole 8, wiring cannot be achieved even if a designed wiring pattern such as the wiring 9 is produced.

In contrast, in the present invention, as described below, by using a device with a drawing function such as an electron beam, fs east ion beam, or laser beam, it is possible to perform drawing with positional deviations corrected and to produce good wiring. .

That is, in FIG. 1(a), the alignment mark 10. is placed in the X area. Alignment marks 11 are also created in the Y area using a stepper in the same process as the wiring holes 6 and 8. By doing so, the position is detected and the pattern shift amount 12 of the Y area with respect to the X area is measured.Next, as shown in FIG. The wiring 14 belongs to the boundary area of the area, and the wiring 15 belongs to the Y area.The divided wiring 13°141 is drawn using the alignment mark 10 of the
5 is drawn based on the alignment mark 11 in the Y area. Finally, based on the previously measured pattern shift 1-Jt12 of the Y area to the X area, a correction pattern 16 is prepared and exposed as shown in FIG. 1(e). By the above method, the wiring hole 6 in the X area, the wiring hole Y in which there is a mutual shift
It becomes possible to wire the wiring holes 8 in the area.

In addition, in the above embodiment, the problem was a connection between areas where a positional shift exists, which was fabricated by a stepper, but the present invention can be applied to all phase L connections of semiconductor integrated circuit devices where a positional shift exists. . For example, by connecting circuit 19 and circuit 1Yia 20 with a semiconductor wafer as shown in FIG. 2, a circuit having one function can be fabricated. l
r! I made 2 approximately 20 total 20, and this was done once.
1820a and circuit 20b. If the upstream circuit N 20 a is defective due to various factors in semiconductor manufacturing, the circuit 19 and circuit 20b can be replaced using the above method.
It is possible to create a chip with a large-scale 1fj'1 circuit that is fully operational.

〔Effect of the invention〕

As explained above, the present invention detects the position of wiring connections in a circuit where positional displacement exists using a device with a drawing function,
By creating a pattern through the procedures of data correction and drawing, it is possible to obtain wiring with high accuracy and free space over the entire surface of the semiconductor wafer.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and is a schematic diagram of the wiring between areas where there is no relative positional deviation between the TVs, which are fabricated by dividing. FIG. , a schematic diagram showing an example of the case where D-positive is applied, FIG. 3 is a schematic diagram of a semiconductor wafer produced by dividing the regions with a stepper, and FIG. 4 is a schematic diagram of the wiring between the regions created by dividing the wafer. In the figure, 6 is a wiring hole in the X area, 7 is a wiring hole in the Y area when there is no positional deviation, 8 is a wiring hole in the X area when there is a positional deviation, 9 is the wiring, and 10 is the
11 is the alignment mark for the Y area, 12 is the pattern shift I for the Y area to the X area.
-Amount, 131. 14 is a wiring that belongs to the EX area, 14 is a wiring that belongs to the boundary area, 15 is a wiring that belongs to the Y area, and 16 is a correction pattern. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1

Claims (1)

[Claims] A method of wiring between semiconductor integrated circuit regions independently fabricated on a semiconductor wafer, wherein the position of the wiring area is detected using alignment marks fabricated within each semiconductor integrated circuit area, and 1. A method of manufacturing a semiconductor device, comprising: detecting a positional displacement of wiring positions between integrated circuit regions; and drawing a wiring pattern by beam scanning while correcting a pattern shift amount according to the positional displacement.