JPS608555B2 - semiconductor temporary storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor temporary memory device that reduces power consumption by performing an effective refresh operation.

Conventionally, capacitors or insulated gate field effect transistors (
A semiconductor temporary memory device that stores information by accumulating it in the gate capacitance of a MOS transistor (hereinafter referred to as a MOS transistor) must rewrite information (hereinafter referred to as refresh) within the temporary memory retention time TA to prevent information from being destroyed due to charge leakage. .

On the other hand, this type of storage device consumes power only when writing, reading, and refreshing information, and the characteristics of the charge leakage vary significantly depending on various conditions such as the manufacturing conditions of the storage device and the operating temperature. In order to ensure safety, refresh was performed at a constant cycle much shorter than the above-mentioned - time memory retention time T^, so even though it is actually refreshed at the time of reading, it is refreshed again immediately after reading. It is often the case that
Therefore, an increase in power consumption was inevitable. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor temporary memory device that reduces power consumption by reducing the number of refreshes by making the refresh cycle approximately equal to the temporary memory retention time of a capacitor memory element.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram explaining the principle of the present invention using a 1-bit temporary storage device as an example to help understand the concept of the present invention.
, E2 and E3, a memory element selection switch S, a write/read selector switch S2, a capacitor memory element CA with a temporary memory retention time of T^, and a voltage E2 and E3 in the figure. After being charged to
The time it takes for the terminal voltage to drop to the threshold voltage VT of the MOS transistor due to charge leakage is TB and T^>
a capacitor CB formed to have the relationship TB;
The sources are connected to the capacitors C^ and CB, the drains are connected to the switch S2 and the power supply E, respectively, and the gate 0 is connected to the switch S. MOS transistors Q^, QB connected to , M whose gate is connected to capacitor CB
OS transistor Qc and information reading DC voltmeter V
and a DC ammeter A to know when IJ is fresh.

), the information stored in the capacitor storage element C^
Although the amount of charge corresponding to 1" is not shown in the voltage between its terminals (V), it is assumed to be equal to or higher than the threshold voltage VT of each MOS transistor constituting the storage device. Therefore, the amount of charge corresponding to the capacitor storage element is The memory retention time TA indicates the time from when it is charged to the voltage E. until it drops to the voltage VT.Next, when forming each element so that the above-mentioned time T^ and TB have a relationship of TA>TB, The second well-known example is
Shown in Figures a and b. Figure a is a plan view of the board, figure b is A-
A cross-sectional view at A′ is shown, and N in the P-type silicon substrate 1 is shown.
Capacitors C^ and CB are formed by mold regions 3 and 5, insulating films 9 and 10 having a film thickness several tenths of that of the surrounding insulating film 11, and metal wirings 12 and 7, and the other side of the capacitor is Metal wirings 6 and 8 in contact with N-type regions 3 and 5, which are electrodes, are connected to a ground point. In this case, the capacitance of each capacitor is assumed to be the same, and the metal wiring 12 is connected to M.
The N-type source region 2 of the OS transistor Q^ is connected to the metal wiring 7.
By making it smaller than the N-type source region 4 of the MOS transistor QB to which it is connected, "The amount of charge leakage from these PN junctions is proportional to the junction area, so
, T^>TB.

The description of write, refresh, and read operations will be continued with reference to FIG. 1 again. First, to write information "1" (or "0"), connect the switch S to the E3 side to make the MOS transistors Q^ and QB conductive, and then connect the switch S2 to the power supply E side (or GND side). When the capacitors C^ and C8 are charged to the voltage E, and the switches S, and S2 are disconnected in this order, the capacitor C^ becomes the information "1".
” (or '10'). As capacitor C8 is charged to voltage E2, MOS transistor Qc becomes conductive and current is supplied from power supply E2 between the source and drain, but immediately after switch S is restored, capacitors CA and CB are When it starts to discharge and the voltage VB of capacitor CB becomes VB<V', the MOS
The current between the source and drain of the transistor is reduced to zero. By using this time as a refresh time and repeating the same operation as writing 3 again, the capacitor C
Information “1” will continue to be stored in ^.

Also, for reading, after connecting the switch S2 to the voltmeter V, connect the switch S to the power supply E3 side to conduct the MOS transistors Q^ and QB, and measure the voltage V^ across the capacitor C^ with the voltmeter V. Reading, VA2VT or V^<V
It learns from either T that the stored information is "1" or "0" and rewrites it to the capacitor C^. At this time, the capacitor CB is charged again to the exposure pressure E, and the time until the next re-fresh operation is TB, so if writing or reading is performed between the previous re-fresh and the next IJ fresh, , the next IJ fresh will occur after a time TB from that point, and if the time TB is formed so that it is almost equal to T^, the temporary memory of the capacitor memory element can be Unlike devices that are refreshed at a constant cycle that is much shorter than the retention time T^, the temporary memory retention time TA of the capacitor memory element can be used as the refresh cycle, reducing the number of refreshes and reducing power consumption. Fig. 3 shows a temporary storage device with a storage capacity of 4 bits in which capacitor storage elements are arranged in a matrix of 2 rows and 2 columns, showing an embodiment of the present invention. Transistor Q,.,R,
．． , Q, 2, R mountain, Q, 3 and Q illusion, Ra, Q2
2, R22, and Q23 are connected to each row line L.2, R22, and Q23, respectively. , L2 are connected to the row line selection multistage inverter 1.

Further, the column lines L3, L selected by the column line selection multi-stage inverter 12 via the MOS transistors Q, . ,Q milk, Q,2,Q
The drain of the MOS transistor is connected to the differential amplifier used for refreshing, and the voltage V, which is equivalent to the threshold voltage of the MOS transistor, is applied to the negative terminal by the power supply EB.
, C2 are connected to each other. On the other hand, "MOS transistors Q,...R,
．． ,Q. Capacitor storage elements M, . ,M,2,Ma,M2
M for applying voltage E (>VT) from power supply E^ to 2.
OS transistors S, . , S, 2, S phantom, and S22 are connected to each other, and furthermore, capacitors M, 3, and M23, MOS transistors Q, 4, and Q24 connected in series, and a power source Ec are provided for each row. An inverter 13 is provided between the power supply Ec and the MOS transistors Q and 4 to read voltage changes and send out a refresh request signal. Next, the operation of writing information "1" into the capacitor storage element M will be explained with reference to the pulse timing diagram shown in FIG.

In the figure, N and P indicate the input terminal and power supply terminal of inverter 1, A and P3 indicate the input terminal and power supply terminal of inverter 12, respectively, and P2 indicates column lines L3 and L5 to be in a floating state. MOS transistor Q,
, indicates the Q-order input terminal.

First, a voltage E (>VT
) to terminals A, and then at timing to, MOS transistors Q4, Q2 are cut off to turn off column lines L3. The body is in a floating state. Next, when the inverter 12 is operated at timing t, since a pulse of voltage amplitude Eo has already been input to the input terminal A, the MOS transistor Q3 becomes conductive and selects the column line L3. Therefore, the voltage E applied to the terminal P4 is input to the positive terminal of the differential amplifier C, producing an output voltage on the output line L, and Z
MOS transistors S, . and S2, are made conductive. At timing t2, inverter 1 is operated and row line L is
When 2 is selected, the MOS transistors Q2, R2, and Q23 become conductive, so that the capacitor storage element Ma and the capacitor M are charged by the power supply E^ to the inter-terminal voltage E2. Next, at timing t3, the row line L3 and the column line - are set in a floating state at timing t4, and then at timing t5, the MOS transistors Q, Q2 are made conductive, and the column lines L3 and L5 are grounded, and the capacitor memory element 2 Writing to the child area is completed.

For reading, the voltage 3 of the capacitor storage element Ma appearing on the column line L between timings t2 and t3 can be changed by applying pulses at the same timing to each terminal as in the case of writing with no voltage applied to the terminal P4. It is done by reading.

At this time, capacitor storage element M and capacitor M are charged to voltage E again. This is essentially a refresh. Conventionally, refreshing would then be repeated at a much shorter period than the temporary 3 memory retention time T of the capacitor storage element), but in the present invention, since the capacitor M23 is provided, As mentioned when explaining the principle explanatory diagram, by making the time TB until the terminal voltage of the capacitor M drops to the four-value voltage VT of the MOS transistor Q24 approximately equal to the above T^, the refresh period can be adjusted to the capacitor. It becomes possible to make the temporary memory retention time T^ of the memory element approximately equal.

With this in mind -2, the refresh operation will now be explained with reference to the pulse timing diagram of FIG.

In addition, the capacitor memory element M river M, 2, Ma, M2
Each of them has been at voltage “E”, “0”, “0” a while ago.
, "E", and in terms of information code, "1", "0"
”, “0”, and “1” are stored.Of course, it goes without saying that the capacitors M, 3, and M23 also accumulate charges that prevent the voltage V8 between their terminals from being lower than the voltage VT. Again, as I have explained repeatedly before,
Temporary memory retention time T^ of each capacitor memory element
"There is a relationship between T^>TB and the time TB from immediately after capacitors M, 3, and M23 are charged to voltage E until the voltage between their terminals drops to the threshold voltage VT of the MOS transistor. , if either capacitor M.3 or M23 falls below the threshold voltage V of the MOS transistor at the same time, either or both of the MOS transistors Q, 4 and Q pin will be cut off, causing the inverter to fail. The voltage of the power supply Ec is input to 13,
The resulting signal drives a circuit that generates timing pulses as shown in FIG. 5 to perform a refresh operation. This circuit conventionally generates a refresh signal at a constant period.

First, at timing to, MOS transistors Q4,,Q
After cutting off the ship's side and putting line line -, L5 in a floating state,
At timing t, inverter L is operated, row line L is selected, and MOS transistor Q phantom, R small Q22, R is activated.
When Q22 and Q23 are made conductive, no voltage appears on the column line L3, but the voltage V of the capacitor storage element ground 2 appears on the column line L5.
^(>VT) appears. Voltage V^ appearing on column line L5
As a result, a voltage is output to the second output line L6 of the differential amplifier, and the MOS transistor S22 becomes conductive. As a result, capacitor storage element M2 and capacitor M23 are charged again to voltage E by power supply E^. Continuing to keep it strictly confidential, when the MOS transistors Q, Q2 are made conductive and the column line SE2- is brought to the ground potential, the refresh of all capacitor storage elements belonging to the row line L is completed. , the voltage is gradually lowered from timing t2 unless writing/reading is performed on the capacitor M, and the voltage is gradually lowered from time T2.
After B, the inverter 12 is driven again to output a refresh request signal.

Next, at timing L', voltage amplitude E is applied to terminal Ao.
After applying the pulse o, the MOS transistors Q4, Q42 are cut off at a certain timing, and the column lines L3 and 5 are turned off.
is in a floating state, and at timing t6, inverter 1,
When operated, row line L, is selected, and MOS transistors Q, . ,R,. ,Q,2,R,2,Q. 3 are applicable. As a result, no voltage appears on column line L5, but on column line L8, capacitor storage elements M, . A voltage V^(>VT) appears, and therefore the voltage output to the output line L4 of the MOSZ transistors S, . is suitable. As a result, the memory elements M, .
and capacitor M,3 are charged again to voltage E by power supply B^. Finally timing t? After turning inverter 1 into a non-operating state and making row lines L and L2 non-selective, MOS transistors Z-stars Q4 and Q2 are made conductive at timing and column lines L3 and L2 are brought to ground potential. Refreshing of all the capacitor storage elements belonging to L, is completed, and the capacitor M,3 starts discharging due to charge leakage from timing t7, and the voltage gradually drops. Note that if the pulse applied to terminal 2 is as shown by the broken line, the row line L
, , L2 are refreshed in this order. Therefore, since the IJ refresh cycle in this storage device is the time TB when no writing or reading is performed, this time TB is set to the temporary memory retention time TA of the capacitor storage element for 2 hours while maintaining the relationship T^>TB. ) are made approximately equal, the refresh period becomes approximately equal to the time T^, making it possible to significantly reduce the number of refreshes. After further refreshing, if writing/reading is performed and capacitors M, 3, and M23 are charged to voltage E again, the next refresh will be delayed, so the number of refreshes will be even fewer. The reduction in power consumption is extremely significant. In addition, in the above embodiment, TA
＞TB to maintain the relationship 3, and T to prevent information destruction of the capacitor storage element during the refresh time.
Of course, the relationship ^-TB>k-to must also be maintained. Therefore, the shorter the time required for refreshing, the closer the time TB can be to the time T^. FIG. 6 shows a temporary storage device with a storage capacity of 1 bit showing another embodiment of the present invention, in which the gate capacitance is expressed as M. and M2 as MOS transistors Q and Q
, o, load MOS transistors Q, , Q, Q5 and MOS transistor Q7, whose gates are connected to the write/read line A. Q, data lines D, D, MOS transistors Q, . and a monostable multivibrator M and a load MOS whose gate is connected to its output line.
Transistors Q2, Q4, Q6 and further the electromotive force is E(>
VT).

In the write operation of this device, first, V is applied to the data line D. (＞
V,) to data line D. After signing (kuVT),
Applying a voltage to selection line A, MOS transistors Q,,Q
When 3, Q5, Q7, and Q are made conductive, the voltage becomes V.
is applied to the gate of the MOS transistor Q. becomes conductive and the potential at point B drops below voltage V, so MOS transistor Q9 becomes cut off, so the potential at point A becomes almost E, and the gate capacitor ground is also charged to voltage E. . On the other hand, the gate capacitance M3 is the MOS transistor Q
5 to approximately voltage E. Finally, when the voltages on the selection line A and the data lines D and D are removed, the writing ends. In this memory device as well, the temporary memory retention time T^ of the gate capacitors M and M2, which are memory elements, is the time TB until the voltage of the gate capacitor M3 drops to the lowest voltage VT indicating information "1". has the relationship T^>TB.

Reading is performed by applying a voltage to the selection line A to make the MOS transistors Q, Q3, Q7, and Q8 conductive, and reading the stored information by the voltage appearing on the data line D. In this case, Since a voltage equal to or higher than the voltage VT appears on the data line D, it can be seen that the data line D is information "1". In the refresh operation, after charges are stored in each gate capacitor, when the voltage of the gate capacitor M3 drops below the voltage VT, a pulse is output from the monostable multivibrator M and the MOS transistors Q2 and Q
, Q is conducted by charging the gate capacitances M2 and M3 to the voltage E again.

This device can perform writing and reading even when the circuit configuration is refreshed. In this memory device as well, the refresh cycle is extremely long due to the gate capacitance M3, and since refresh is also performed at the same time as reading is performed, it is possible to reduce the number of refreshes and reduce power consumption. As described above, the present invention is extremely effective in providing a semiconductor temporary memory device in which the refresh period is approximately equal to the temporary memory retention time of the capacitor memory element, thereby reducing the number of refreshes and reducing power consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIGS. 2 a and b are a plan view and a sectional view of a capacitor storage element, FIG. 3 is a diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are Pulse timing diagram FIG. 6 is a diagram showing another embodiment of the present invention. In the figure, CA, M, . ,M,2,M2・,M2,M
・,M2...Capacitor storage element, Cs,M,3,
FuZ3, gunwale...capacitor, Q^, QB, Qc, Q,,
Q2, QI・, Q12, Q21, Q2, Q13, Q bad,
RI・,R12,R21,R22,SI・,SI2,S
21, S Kyou, Q41, Q Umbrella, IQ, Q4. Q5, Q6
,Q,false,Q,. ．． ．． ．． ...M06 transistor, E,, E2, E3, E^
,E8,Ec,E...power supply, M...monostable multivibrator, C,,C2...differential amplifier, 1,,2,
13... Inverter, L,, L2... Row line, L3
, L5... Column line, L, L6... Output line, A...
・...Selection line, D, D...Data line, P,, P2, P3,
P4, Ao, A, ...terminal, S,, S2 """ switch. Mathematics 1 Figure 2 Figure 3 Groove 4/History 5 Figure *5 Figure

Claims (1)

[Claims] 1. A semiconductor temporary memory device in which information is written by storing an amount of charge corresponding to information "1" or "0" in a capacitor storage element, which is equipped with a capacitor capable of storing charge during writing and rewriting, and 1. A semiconductor temporary storage device, characterized in that rewriting to the capacitor storage element is controlled by detecting the amount of charge stored in a capacitor.