JPS608504B2 - Collective reaction analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a group reaction analyzer used for group learning, etc., which is composed of a base unit and a plurality of slave units, and in particular, the base unit transmits a signal at a period of an integral multiple of the number of pre-set units N. A pulse train signal from the base unit is sent to each slave unit, and each slave unit is operated in sequence so that a response signal can be sent to the base unit every 1/N of the pulse train. The answer output is obtained by superimposing the answer signal obtained from the device and comparing and detecting the superimposed signal with the output from the control signal generation circuit in the parent device. By simplifying the connection method between machines by using a minimum number of two wires, and ensuring synchronization between each slave unit without using a separate synchronization signal, and by providing a rectifier circuit in each slave unit, The necessary power is obtained for the slave unit from the pulse train signal of the machine, there is no need to provide a separate power line, and the pulse train signal of an integral multiple of the number of slave units functions as a power signal, a control signal, and a synchronization signal. The purpose of this study is to provide a new group reaction analyzer that uses the following methods.

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, A is the main unit, (Bi) (i=1, 2...
. . . n) are a plurality of slave units, for example eight (n=8), which are connected by two connection lines 1 and 2.

In the main unit A, 3 and 4 are DC power input terminals, 5 and 6 are output terminals connected to the connection lines 1 and 2, and the input terminal 4 and the output terminal 6 are grounded, and the input terminal 3 A gate circuit 8 is inserted between the output terminal 5 and the output terminal 5.

An example of the gate circuit 8 includes Darlington-connected transistors 9 and 10. The collector and emitter of the transistor 9 are connected to the input terminal 3 and the output terminal 5, respectively, and the base of the transistor 10 is grounded via a constant voltage diode 11. On the other hand, the collector of a transistor 13 whose collector is connected to the input terminal 3 via a bias resistor 12 and whose emitter is connected to the ground is connected to the base of the transistor 10, and the base of the transistor 13 is connected via a resistor 14 and an inverter 15 to control the control described later. Signal generation circuit 2 is connected to this circuit and turns on/off the DC voltage from input terminal 3 according to the control signal.
Turn off.

The control signal generation circuit 20 supplies a clock pulse generator 2 to generate a clock pulse CP of, for example, 10 to 30 KHz.
1, a BCD counter 22 that counts its clock pulses CP, an 8-signal counter 23 to which the output of this counter 22 is supplied, a 1G counter 24 to which the first stage output of this counter is supplied, and a 1G counter 24 to which the output of this counter is supplied. a negative logic AND circuit 25 to which the outputs of items 9 and 1 are respectively supplied to the input side; and a NAND circuit 2 to which the output of this AND circuit 25 and the clock pulse CP are supplied to the input side.
6, for example, five lock-type normally open switches S, -S5 each having one end connected to the second to sixth output ends of the counter 23 and terminals connected to each other. (not shown), high level and low level signals are supplied to the J and K input terminals, respectively, and the output of the AND circuit 25 is supplied to the clock input terminal C. A J/K flip-flop 29 and a J/K flip-flop whose positive and negative output terminals Q and Q are supplied to input terminals J and K, respectively, and whose clock input terminal C is supplied with the output of the switch circuit 28. It consists of a flip-flop 30 and a NAND circuit 31 whose input side is supplied with the output of the flip-flop 30 and the output of the NAND circuit 26, and from the NAND circuit 31 a control signal CK consisting of a periodic pulse train is obtained.

Although a high level input is always supplied to the clear terminals CL of the flip-flops 29 and 30, the input becomes low level when the feedback normally open switch SF inserted between the clear terminal CL and the ground is closed. In this case, the counter 23, correct answer setting switch 28, flip-flop 29,
30 and the feedback switch SF constitute a feedback signal forming circuit 32.

The parent device A also has a comparison circuit 40 that compares the output VC of the gate circuit 8 and the output obtained by inverting the output Ck of the control signal generation circuit 20 via an inverter 34.

An example of this circuit is one in which the base has a relatively high resistance value (e.g. 1
NPN whose collector is connected to the positive power supply through a resistor 42, and whose emitter is connected to the ground through a resistor 41 of several kilohms) to the emitter of the transistor 9 of the gate circuit 8.
A resistor 41 is inserted between the type transistor 43, the connection midpoint of the resistor 41 and the emitter of the transistor 9, and the ground.
A constant voltage diode 45 is inserted between a resistor 44 having a higher resistance value, a connecting midpoint between the bases of the resistor 41 and the transistor 43, and the ground, and one input side is connected to the transistor 4.
3 and an exclusive OR circuit 46, the other of which is connected to the inverter 34, and resistors 41 and 4.
4 maintains the connection line 1 at high impedance, and the output P of the OR circuit 46 is connected to the analyzer body 53, which includes an attendance/absence memory 50, a circuit display device 51, and an answer data processing device 52 that calculates the correct answer rate, etc. supplied to Although detailed explanation will be omitted, the analyzer main body 53 is supplied with the output Ck of the control signal generation circuit 20, and uses this and the output P of the OR circuit 46 to determine the response status of the slave unit Bi, that is, the slave unit The correct answer setting switch circuit 28 determines the answer number of
The output PS of
The configuration is such that the correct answer can be determined based on the output P of . As shown in FIG. 1, an example of the slave unit Bi is set on a predetermined tabletop and includes a relay unit RC that controls the transmission timing of the answer signal of the slave unit, and an answer unit connected to this unit that emits the answer signal Va. It is composed of a selection unit ST.

The relay unit RC has input/output terminals 61, 62, 63, 64 connected to the connection lines 1, 2, and the terminals 62, 6
4 is grounded, and a power supply circuit 6 consisting of a half-wave rectifier circuit consisting of a diode 65 and a capacitor 66 is connected to a terminal 61.
7 is connected, and a DC power source obtained based on a pulse train VC, which will be described later, sent out from the base unit A is supplied to each element or circuit in the relay unit as an operating power source.

A gate circuit 68 is inserted between the terminals 61 and 63, and has a diode 96 that passes the pulse milk WC, and a PNP type transistor 70 whose emitter and collector are connected in parallel to this diode 96. An answer signal Va from an answer selection unit ST, which will be described later, is transmitted to the base unit A through conduction.

71 is a control circuit for controlling conduction of the transistor 70, and is connected to an octal ring counter 75 connected to the terminal 61 through a diode 72 and, if necessary, a voltage dividing circuit of resistors 73 and 74, and connected to the first stage output terminal thereof. A similar octal counter 76 with a diode 78 and a resistor 7 at terminal 61.
Inverter 80 and diode 78 connected via 9
and a resistor 81 connected in parallel between the resistor 79 and the ground.
and a counter reset circuit 84 having a charging/discharging circuit 83 consisting of a capacitor 82.
counter 76 corresponding to that suffix digit
The output terminal of the transistor 70 is connected to the base of the transistor 70 via an inverter 86 and a resistor 87.

Therefore, regarding the relay unit RC of slave unit B, Counter 7
5, an output is obtained from the output terminal, and this is supplied as an input pulse to the counter 76. Therefore, a high level control signal is obtained from the first stage output terminal of this counter 76, and this is applied to the inverter. 86 to the base of the transistor 68, the transistor 70 becomes conductive, and this state continues until the next pulse arrives from the counter 75, that is, until the counter 75 counts the ninth pulse of the pulse train VC. Ru. Similarly, for slave unit B2, &......&, the pulse train VC is 9th to 16th, 17th to 24th, 57th to 64th.
The second interval transistor 70 is suitable. The answer selection unit ST also has terminals 91 and 92 connected to the terminals 63 and 64 of the unit, a power supply circuit 67, and a counter 7.
5 and its reset circuit 84, a power supply circuit 94, a counter 95, a reset circuit 96, and one end connected to the counter 9.
5 lock-type normally open switches SA, ~SA5, which are connected to the second to sixth output devices of 5, respectively, and whose terminals are connected to each other;
An answer option switch circuit 97 having these lock release push pins (not shown) is connected to an inverter 98 to which the output thereof is supplied, and the inverter output conducts the circuit to send a positive power source to the terminal 91 as an answer signal Va. It has at least a PNP transistor 99 as a gate circuit.

In addition, 100 is a feedback display circuit, and is a negative logic inverter 10 connected to the output side of the inverter 98.
1, a positive logic inverter 103 connected to its output side via a resistor 102, the resistor 102 and the inverter 10
A charging/discharging capacitor 104 connected between the connection midpoint of No. 3 and the ground, and a light emitting diode 106 as a display element and a protective resistor 107 inserted between the output side of the inverter 103 and the positive power terminal 105. have The operation of the apparatus of the present invention configured as described above is as follows.

Now the switch S of the correct answer setting switch circuit 28 of the base unit A, ~
It is assumed that S5 and the feedback switch SF are not pressed, that the switches SA, ~SA5 of the answer option switch circuit 97 of the slave unit Bi are not pressed, and that each counter of the base unit and the slave unit is in a reset state. In this state, since the flip-flop circuits 29 and 30 of the control signal generation circuit 20 of the base unit A are all cleared, the output F2 of the negative output terminal Q of the flip-flop circuit 30 is as shown in FIG. Maintain high levels as shown.

Therefore, in this state, the clock signal generator 21 outputs the time to
When the clock pulse CP is obtained as shown in FIG. 2A, outputs T, .
T8 is obtained, and the ninth value of the counter 24 is filled with the output T.
As shown in FIGS. 2C and C2 from the tenth output terminal, from the time t64 when the 6th pulse of the clock pulse CP is obtained to the time t72 when the 73rd pulse is obtained, and from the time t72 to the 81st pulse From the moment the pulse is tied o
The output U9, U, which is at the high level in the section. is obtained from the AND circuit 25, as shown in FIG. 2D.
From the high level of the section 4, the low level of the section from 4 to t, from the time o to t, the high level of the section 44, etc.
An output R, which periodically repeats high and low levels, is obtained. Based on this, the second
As shown in Figure E, the output R is the inverted output of the clock pulse CP in the high level section, and the output R is at the high level in the low level section.
2 is bound. Therefore, as shown in FIG. 2, from the NAND circuit 31, since the output F2 of the flip-flop 30 is at a high level, an inverted output of the output R2 of the NAND circuit 26 is obtained, and this is sent to the gate circuit 8 as the control signal Ck. The input terminal 3.4 is supplied from this circuit 8 as shown in FIG. 2J.
A DC power supply (for example 9 volts) supplied to V is gated by a control signal Ck to obtain a periodic pulsed voltage Vc as a control, power supply and synchronization signal in phase with the control signal Ck, which is applied to terminals 5, 6 and connection lines 1 and 2 to each slave unit Bi. Therefore, each child armor i is supplied with the pulsed voltage Vc, so that its power supply circuit 67
, 94, the device is activated, and the first pulse of the pulsed voltage Vc opens the gate circuit 68 of the relay unit RC of the handset B as shown in FIG. Selection switch SA
．． ~S is not pressed, so the answer signal Va is the second
As shown in FIGS. L1 to L8, the output P remains at a low level as shown in FIG. 2M.

Similarly, every 8 bits of the pulsed voltage Vc are sequentially
, B...B6 becomes conductive as shown in FIG. 2 K2 to K8, and repeats the same operation as described above. Then, the pulsed voltage Vc becomes 64th pulse and after the time t
63 to time t8. When the zero-bell period in between arrives, the voltage between the terminals of the capacitors 82 of the reset circuits 84 and 96 of each slave unit Bi drops to zero, and the output RP of the inverter 80 decreases from time t63 as shown in FIG. 2N. 7, minutes (7
, is the time required for the charge in the capacitor 82 to discharge through the resistor 81, which is more than half a cycle of the pulse Vc), and becomes a low level at time t65, which resets the counters 75 and 76, and the master unit and slave unit You can synchronize with the machine. In addition, during the repeated pulse section of the pulse-like voltage Vc, the capacitor 82 is repeatedly charged and discharged by the high and low levels of the pulse, so that no reset signal is substantially obtained. In this state, first of all, to check the attendance of the slave unit Bi, for example, the correct answer setting switch S of the base unit A.
, and have the attendees on each slave device press the answer option switch SA. In this way, the pulsed voltage Vc is sent from the base unit A to each slave unit, and the gate circuit 68 of the relay unit RC of each slave unit is activated every time nine pulses of the pulsed voltage arrive. They are opened one after another, and the handset B
, the gate circuit 68 is opened at the time when the first pulse of the pulsed voltage Vc is obtained, and the output from the second stage output end of the counter 95 becomes high level at the time when the second pulse is obtained. , switch SA, is on, transistor 99 is conductive through which FIG.
As shown in the figure, a response signal Va consisting of a positive DC voltage of one cycle section of the pulsed voltage yc is sent to the base unit A side.

Due to this answer signal Va, the voltage in the "0" level section between times t' and 2 of the pulsed voltage Vc of the base unit A increases as shown in FIG. As shown in FIG. 2M, a pulse output P is obtained from the circuit 46 at a time point t corresponding to the answer signal Va, and this and the output T2 of the counter 23 obtained through the correct answer setting switch 28 are stored in a repeated pulse train section of the pulsed voltage Vc. By comparing the output of the memory circuit 111 with the output of the memory circuit 111 by the comparison circuit 110, an output M representing the attendance of the slave unit B can be obtained. Similarly, the pulsed voltage Vc is applied to slave units B2 to B8 as well.
An output representing attendance/absence can be obtained sequentially every nine pulses.

Note that in the case of absence, no response signal is obtained, so the output P of the OR circuit 46 remains at a low level. Then, the output M representing attendance is stored in the attendance/absence memory circuits 5 provided as many as the number of handsets (8), and thereby the gate circuits 112, 11
3, and transmits the answer status to the questions described below only for the present handset to the answer display device 51 and answer data processing device 52, which display the correct answer, wrong answer, or answer status for each handset.

To ask a question next, press the correct answer setting switch for that question, for example S3, and have the attendees of each slave unit Bi press whichever answer option switch SA, ~SA5 seems to be the correct answer for the question. .

In this way, when the output of the counter 95 corresponding to the pressed option switch is obtained, the answer signal Va
is sent to the parent device A side, and at that point, an output P is obtained from the OR circuit 46. Next, a so-called feedback function will be described in which the feedback lamp of only the handset whose correct answer option switch is pressed is turned on. For example, suppose that the correct answer setting switch S3 of the base unit is pressed and the answer switch SA3 of the slave unit is pressed.In this state, for example, at a certain point in time, close the feedback switch SF as shown in FIG. For example, the clear state of flip-flops 29 and 30 is released.

However, in this state, the outputs F1 and FI of the output terminals Q and Q of the flip-flop 29 maintain low and high levels, respectively, since no signal is supplied to the clock terminal C.
Therefore, even if the output from the counter 23 is supplied to the clock terminal C of the flip-flop 30 via the switch S3, the output terminal Q remains at a high level. Then, time t8. When the output RI of the AND circuit 125 becomes a high level as shown in FIG. 2D, the outputs F1 and FI of the flip-flop 29 are inverted and become high and low levels, respectively, as shown in FIG. 2 GI and G2. Since the output T3 from the counter 23 is supplied to the clock terminal C of the flip-flop 301 through the switch S3 at time t33, the output F2 is inverted to a low level as shown in FIG. 2H'. On the other hand, the output Ck of the NAND circuit 31
As shown in FIG. 2, the output of the flip-flop 30 is at a high level between times t8o and t83, so three pulses, which are the inverted outputs of the pulse output R2 of the NAND circuit 26, are obtained during this period, and the output of the flip-flop 30 is at a high level. A feedback signal that becomes high level is obtained at the time point t when the output F2 becomes low level, and therefore a pulsed voltage Vc' similar to this feedback signal is sent to each child unit Bi as shown in FIG. 2 J'. .

Based on this, the counter 95 of each slave unit counts only four pulsed voltages Vc, so a continuous output is obtained from the fourth output terminal, and if the selection switch S is pressed, this output is output from the capacitor. 04 is charged, the output side of the inverter 103 becomes a low level, and the light emitting diode 106 lights up to indicate that the answer is correct.

Note that in this lighting state, the output of the switch circuit 97 is at a low level, and the charge in the capacitor 104 is transferred to the resistor 1.
02 and the transistor or C-M in the inverter 101
It is released by being discharged through the OS. Incorrect answer: For example, when switch S is closed, pulsed voltage y
At the second pulse of c, the output of the counter 95 is switched to the switch S.
A. The capacitor 104 is charged through the inverter 98. In this case, the width of the counter output is one cycle of the pulse voltage, so the capacitor 104 is charged through the inverter 98.
Even if it is charged to 4, as soon as the output becomes zero, the resistor 1
02 and the transistor or C-M in the inverter 101
It is discharged through the OS, so the light emitting diode 106 does not light up, and if the switch SA and subsequent switches are closed, no counter output is obtained.
Of course it won't light up.

As described above, according to the device of the present invention, the control signal from the base unit,
A pulsed voltage that serves as a power signal and a synchronization signal is sent to each pre-device, and each slave unit sends a response signal consisting of a DC voltage to the master unit, which changes the level of the pulsed voltage and responds. Since the main unit and each slave unit can be connected to each other with a minimum number of two connection lines, the main feature is that the installation work can be easily carried out. Also, since the DC voltage is gated with a control signal to make a pulse with the same phase and level as the control signal and the power signal, and this is rectified in the slave unit to obtain the DC power, it is not necessary to use the power signal as the control signal. No complicated circuit is required for superimposition, and the configuration of this demultiplexer is simplified. Furthermore, the pulsed voltage from the base unit has a rest period between periodic pulse trains, and each counter of each slave unit is reset during this interval, so the synchronization between the base unit and each slave unit is ensured. done reliably,
There is no risk of malfunction.

Further, as in the above example, by increasing the impedance of the connection line in the comparator circuit, the response signal can be reliably detected without malfunctioning even if the power supply circuit of the slave device is a half-wave rectifier circuit.

Furthermore, by configuring each handset with a relay unit having an answer signal gate circuit and an answer selection unit as in the above example, the relay unit can be installed at a predetermined position and the answer selection unit can be made compatible. It has features such as being portable.

In the above example, we have explained the case where the handset is composed of a relay unit and an answer selection unit in order to provide compatibility with the handset, but in the case of a fixed type, the corresponding parts in Figure 1 are the same. As shown in FIG. 3 with reference numerals, the relay unit in FIG. 1 is omitted, but the first stage output of the counter 95 of the answer selection unit ST is supplied as an input signal to the octal counter 76, and each stage of this counter 76 The output of the counter 76 may be supplied to the gate circuit 68 via the inverter 86 as in the case shown in FIG. Compared to the configuration shown in the figure, one counter and its reset circuit can be omitted, and the configuration of the slave unit can be simplified.

Furthermore, in each of the above-mentioned embodiments, the case where the number of handsets is eight and the number of options is five has been explained, but the number of handsets and the number of options can be selected to any desired number, and the number of choices can be selected as desired. Depending on the number of slave units N and the number of choices M (where M is 2 or more), select the number of pulses N×M of the pulse train of the control signal generation circuit 20 of the base unit and change the number of steps of the counters 76 and 95 of the slave unit. Just do it.

Furthermore, as shown in FIG. 4, one control signal generation circuit 20, a plurality of gate circuits 8 and comparison circuits 40, and slave units
By arranging the sets of , it is possible to increase the number of slave devices without increasing the answer recognition time.

Furthermore, in the control signal generation circuit 20, the number of pulses in the pulse train does not have to be strictly N×M, but may be at least N×M, and the pause period between adjacent pulse trains is also equal to the number of clock pulses. It does not need to be 16 bits, and it is sufficient to obtain enough time for the counter reset circuit of each child device to operate.

In addition, the switches 28 and 97 of the master unit and each slave unit include switches S, -S5 and SA. ~ If normally closed switches S6 and SA6 are arranged in parallel with SA5 and are opened by these presses, and one end of the switch is connected to the seventh output terminal of the counter 28 and the sixth output terminal of the counter 95, the This switch S when answering
An unanswered signal can be obtained through A6. Furthermore, the input side of the counter 24 is connected to the final stage output terminal of the counter 23 of the control signal generation circuit 20 of the master unit, and the switches S and -S5 of the switch circuit 28 are shifted one by one to the previous stage side in accordance with this. , the same effect as in the above example can be obtained even if the switches S, to S5 of the answer selection switch circuit 28 of each child unit are shifted one by one to the subsequent stages, in short, the switch circuit 28 It is sufficient if the counter output immediately before is supplied to the counter 24.

Furthermore, a delay circuit for one bit of the clock pulse CP is inserted on the output side of the AND circuit 25 of the control circuit 20 of the parent unit, and the response selection switch S beside each slave unit is accordingly inserted.
Even if A, -SA5 are connected to the first to fifth output stages of the counter 95, respectively, the same effect as in the above example can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a systematic connection diagram showing one embodiment of the device of the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, FIG. 3 is a diagram showing another example of the slave unit, and FIG. FIG. 2 is a block diagram illustrating an embodiment when a large number of slave units are connected to a base unit. A is the main unit, B~& is the slave unit, 3 and 4 are DC power input terminals,
8 is a gate circuit, 2 river control signal generation circuits, 40 is a comparison circuit, 53 is the analyzer main body, RC is a relay unit, ST
1 is an answer selection unit, 65 and 94 are power supply circuits, 68 is a gate circuit, 71 is a control circuit, 95 is a counter, 97 is an answer selection switch circuit, and 99 is an answer signal sending circuit. Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] 1. In a collective reaction analyzer consisting of a parent device and a plurality of N child devices, the parent device has an input terminal to which DC power is supplied, and a gate circuit connected to the input terminal. a control signal generation circuit that periodically generates a pulse train that is an integral multiple of the number of handsets N and controls the gate circuit; an output terminal of the gate circuit and the control signal connected through the output terminal; and a comparison circuit that compares the output of the generation circuit, and each slave unit has an input terminal connected to the output terminal of the parent unit, and a power supply circuit that rectifies the input pulse supplied to the input terminal. , an answer selection counter that counts the pulses, an answer selection switch connected to each output terminal of the counter, and an output from the power supply circuit as an answer signal in accordance with the output from the answer selection switch. an answer signal sending circuit that sends out the answer signal to the terminal; a gate circuit that gates only the answer signal inserted between the input terminal and the answer signal sending circuit; and a control circuit for controlling conduction of the gate circuit, and the gate circuit of each slave unit is sequentially controlled to be conductive every 1/N of the input pulse, and the gate circuit of each slave unit is controlled to be conductive in turn in response to a response signal of each slave unit from the comparison circuit of the base unit. A group reaction analysis device characterized in that a response output is obtained. 2 The control circuit of each slave unit counts the input pulses.
and a second counter to which the first stage output of the first counter is supplied, and the control signal is obtained from a predetermined output stage of the second counter. Analyzer as described in section.