JPS6083416A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain a delay circuit which generates a rising and a falling pulse synchronizing with a control signal by adding a differentiating circuit and a leading edge trigger type FF to a comparator for delay pulse wave generation. CONSTITUTION:This delay circuit consists of the differentiating circuit composed of a capacitor 11 and a resistance 12, trigger circuit composed of an NPN transistor (TR), differentiating circuit composed of a capacitor 14 and a resistance 12, trigger circuit composed of an NPNTR16, comparator 100 for delay pulse wave generation, differentiating circuit composed of a capacitor 17 and a resistance 18, trigger circuit composed of an NPNTR19, and leading edge type FF200. Consequently, the delay circuit generates the rising delay pulse and falling delay pulse synchronizing with the control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a delay circuit using charging and discharging of a capacitor. ◎ Figure 1 shows a conventional delay circuit. It has a terminal 3 and an output terminal 4, and the control terminal 1 is connected to an NPN via a capacitor lit.
) The base of the transistor 13 and the resistor 12 are connected.@The other end of the resistor 12 is connected to the ground terminal 3. N
The emitter of the PN transistor 13 is connected to the ground terminal 3, and the collector of the NPN transistor 13 is connected to the series connection point between the constant current source and the capacitor 20. The input terminal '5 of the comparator 100 is further connected to this series connection point. A reference voltage terminal 6 of the comparator 100 is connected to the ground terminal 3 via a reference voltage source 30. The other end of the constant current source 40 is connected to the power supply terminal 2, and the other end of the capacitor 20 is connected to the ground terminal 3. A current is supplied to the comparator 100 via a constant current source 50'ft, and the output of the comparator 100 is connected to the output terminal 4.

Next, the operation will be explained with reference to the signal waveforms shown in FIG. When a control signal is applied to the control terminal l, a differential waveform is generated by the capacitor 11 and the resistor 12. This differential waveform is NP.
When a sufficient current is supplied to the base of the NPN transistor 13, the NPN transistor 13 is not saturated, and the input terminal 5 of the comparator 100 becomes the collector-emitter saturation voltage of the NPN transistor 13. Therefore, the voltage at the output terminal 4 becomes low level. At the same time, capacitor 20 is discharged. (NPN) When no current is supplied to the base of the run raster 130, this NPN transistor 13 is turned off, and the constant current 40 is turned off, and the capacitor 20 is turned off.
is charged. This charging voltage is supplied to the input terminal 5 of the comparator 100, and the reference voltage VBI of the reference voltage source 30
When the voltage exceeds CF, the output terminal 4 becomes high level. When the input terminal 5 of the comparator 100 is at a low level,
The delay time is until the reference voltage vR r'lt is exceeded.

When such a delay circuit is used, as is clear from the signal waveform in Figure 2, the delayed pulse at the rising edge is output, but the delayed pulse at the falling edge is not synchronized with the control signal and the delayed pulse at the falling edge is output. ◎ Also, in order to use this delay circuit to output the inverter output of the control signal, there is a drawback that two charge/discharge sensors and a comparator are required. An object of the present invention is to provide a delay circuit that can generate delay pulse waves at rise and fall synchronized with a control signal with a relatively simple circuit configuration. This device is characterized by adding a differentiating circuit and a leading edge trigger type 7 lip-flop (hereinafter referred to as F-F) to the comparator. A delay pulse can be generated, and a comparator for generating delay pulses can be connected to Q1 by combining two or more differential paths.
The differential circuit inserted between the co/parator output terminal and F@F can be deleted, and the inverter signal of the control input signal can also be generated by a common charging/discharging capacitor and a common comparator.

The circuit of the present invention preferably includes a differentiating circuit between the control terminal and the input terminal of the comparator, and further connects the comparator output terminal to the input terminal of F-F via the differentiating circuit and the trigger transistor. It is characterized in that the input terminal at the other end of FF is connected to a control terminal. : Hereinafter, the present invention will be explained in detail with reference to the drawings.

： FIG. 3 is a circuit diagram of one embodiment of the present invention.

Components 9 that are the same as those in the conventional example shown in FIG. , reference voltage terminal 6, comparator output terminal 4. F-F
It has an output terminal 7.

The control terminal l is connected to the D input of the F"F200, and further connected to the connection point between the base of the NPN h run raster 13 and the resistor 12 via the capacitor 1ift, and also to the base of the NPN transistor 16 via the inverter 60 and the capacitor 14. The emitter of the NPN transistor 13.16 and the other end of the resistor 12.15 are connected to the ground terminal 3.
The collectors of the PN transistors 13 and 16 are commonly connected to the connection point between the constant current source 40 and the capacitor 20, and this connection point is connected to the input terminal 5 of the comparator 100. The reference voltage terminal 6 of the comparator 1000 is connected to the ground terminal 3 via a reference voltage source 30ft. The other end of the constant current source 40 is connected to the power supply terminal 2, and the capacitor 20
The other end is connected to ground terminal 3. Comparator 1
Output terminal 4 of 00 is connected to capacitor 171r via NP.
It is connected to the connection point between the base of the NPN transistor 19 and the resistor 15, and the emitter of the NPN transistor 19 and the resistor 1
The other end of 5 is connected to the ground terminal 3. The collector of the NPN transistor 19 is FF200:>CKi
Connected to child.

That is, the circuit of this embodiment includes a differential circuit using a capacitor 11 and a resistor 12, and an NPN)
1) A trigger circuit consisting of a trigger circuit, a differentiator circuit consisting of a capacitor 14 and a resistor 15, and a trigger circuit consisting of an NPN transistor 16, a converter 100, a capacitor 17, and a resistor 18 to differentiate the control input signal. It is composed of a trigger circuit consisting of a transistor 19 and an F@F transistor.

Next, the operation will be explained with reference to the signal waveform shown in FIG. 3. When a control signal is applied to the control terminal 1, a differential waveform is generated between the capacitor 11 and the resistor 12.

When a sufficient current is supplied to the base of the NPN transistor 13, the NPN transistor 13 becomes saturated and the input terminal 5 of the comparator 100 becomes NPN.
N) Becomes the saturation voltage of the collector emitter IIJI of the transistor 13. Therefore, the output terminal 4 of the comparator 100
becomes low level and capacitor 2o is also discharged◎N
When current is no longer supplied to the pace of the PN) transistor 13, this NPN) transistor 13 is turned off and the constant current 4
o, the capacitor t20 is charged. When this charging voltage, that is, the voltage at the input terminal 5 of the comparator 100 exceeds the reference voltage V R of the reference voltage source 3o, the output terminal 4 of the comparator 100 becomes high level.
This high level signal is differentiated by a capacitor 17 and a resistor 18. This differential waveform is NPN) transistor 19
When the base of F-F200 is fully biased to saturate the transistor 19, the CK terminal of the F-F200 becomes the collector-emitter saturation voltage of the NPN transistor 19. Therefore, the trigger is applied to F@F200, and the D of 9F@F200
The state of the terminal is output from the 0 terminal, and as a result, the output terminal 7
A high level output signal is output from.

When the control signal at the control terminal l becomes low level, a differential waveform is generated by the capacitor 14 and resistor 15 through the inverter 60. Therefore, NPN) transistor 16
turns on and reaches saturation.

As a result, the input terminal 5 of the comparator 100 is NPN
The collector-emitter saturation voltage of the transistor 16 is reached, and the output terminal 4 of the comparator 100 becomes low level. When the NPN transistor 16 is turned off, the capacitor 20 is charged with a constant current 40, and when the charging voltage exceeds the reference voltage vRP, F of the reference voltage source 30, the output terminal 4 of the comparator 100 becomes high level again. This high level output is differentiated by a capacitor 17 and a resistor 18 to generate a differential waveform, and an NPN transistor 19 is turned on. Therefore, a trigger is applied to the >CK terminal of F-F200, and the state of the D terminal of F@F200 is output to the Q terminal, and as a result, a low level output signal is output from the output terminal 7.

Finally, there is no delay time until the input terminal 5 of the comparator 10o exceeds the reference voltage VRIF't- from the low level, and at the time of the fall of the control signal, it is better to pass through the entire inverter 60. An output with the same delay time and fall delay time can be generated.

FIG. 5 shows another embodiment of the present invention, in which the same components as those in FIG. 3 are designated by the same numbers and their explanation will be omitted. The interesting part is that the output of the comparator 100 is received by the transistor 19 without going through a differentiating circuit, and the second F
@F200 ``k is provided・F-F200
') is connected to the collector of the transistor 19, its D terminal is connected to the inverter 60, and its Q terminal is connected to the second output terminal 7'.

According to this circuit, as shown in the signal waveform in FIG.
Just by providing the 20th F@F200', the output terminal 7
A complementary second output signal is obtained.

As described above in detail, according to the present invention, a delay circuit can be obtained in which the rising and falling times of the delayed pulse match the control signal, and furthermore, it is possible to reduce the number of F-F to two. in,
A delay circuit that can easily output a control signal from a delayed inverter can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a conventional circuit diagram, FIG. 2 is a signal waveform showing conventional operation, FIGS. 3 and 5 are circuit diagrams showing the first and second embodiments of the present invention, respectively, and FIG. 6 are signal waveform diagrams showing the operations of the first and second embodiments, respectively. 1...Control terminal, 2...Power terminal, 3
...Ground terminal, 4...Comparator output 7 [1, 5...Comparator input terminal, 6...
...Comparator reference voltage terminal, 7.7'...
・・F-F output terminal, ] 1, l 4゜17.20
・・・・・・Capacitor, 12,15.18゜105・
...Resistance, 13.16.19...NPN
Transistor, 3o・old・Reference voltage, 40.50・
Old...Constant current, 60...Inverter, 100...
...Comparator, 200, 200'...
- Leading edge trigger type 7 lip flop. Mistake / Figure Z Figure 7 Punishment-1 Line 3 Figure

Claims (1)

[Claims] (1) It has a capacitor, two switch circuits that control charging and discharging of the capacitor, a comparator that compares the charging and discharging voltage of the capacitor with a reference voltage, and a slip/frog circuit. A control signal is applied, a signal obtained by inverting the phase of the control signal is applied to the other switch circuit, and the level of the signal is outputted via the flip-flop circuit in response to the output of the comparator. Features a delay circuit.